Semiconductor device and method of forming the same
AssigneePowerchip Semiconductor Manufacturing Corporation
InventorMeng-Han Lin
Life of this patent
Estimating the term…
Abstract
A semiconductor device and a method of forming the same are provided. The semiconductor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; a source region and a drain region in the semiconductor substrate and on opposite sides of the gate structure; a sacrificial oxide layer on the semiconductor substrate; a contact etch stop layer on the sacrificial oxide layer; a lower interlayer dielectric layer on the contact etch stop layer; a high resistance dielectric layer on the gate structure and the lower interlayer dielectric layer; and a high resistance field plate, wherein at least a part of the high resistance field plate is on the high resistance dielectric layer.
Claims20
A semiconductor device, comprising:
- a semiconductor substrate;
- a gate structure on the semiconductor substrate;
- a source region and a drain region in the semiconductor substrate and on opposite sides of the gate structure;
- a sacrificial oxide layer on the semiconductor substrate;
- a contact etch stop layer on the sacrificial oxide layer;
- a lower interlayer dielectric layer on the contact etch stop layer;
- a high resistance dielectric layer on the gate structure and the lower interlayer dielectric layer;
- and
- a high resistance field plate, wherein at least a part of the high resistance field plate is on the high resistance dielectric layer.
A method of forming semiconductor device, comprising:
- providing a semiconductor substrate;
- forming a gate structure on the semiconductor substrate;
- forming a source region and a drain region in the semiconductor substrate and on opposite sides of the gate structure;
- forming a sacrificial oxide layer on the semiconductor substrate;
- forming a contact etch stop layer on the sacrificial oxide layer;
- forming a lower interlayer dielectric layer on the contact etch stop layer;
- forming a high resistance dielectric layer on the gate structure and the lower interlayer dielectric layer;
- and
- forming a high resistance field plate, wherein at least a part of the high resistance field plate is on the high resistance dielectric layer, and wherein another part of the high resistance field plate is in the high resistance dielectric layer and in the lower interlayer dielectric layer.
Dependencies are inferred from the claim text.