Method for manufacturing semi-floating gate transistor

A method for manufacturing a semi-floating gate transistor, comprising the following steps:

• S1:
• providing a semiconductor silicon substrate, wherein,
• in a first region of the semiconductor silicon substrate, the semiconductor silicon substrate is isolated by multiple strips of X-direction field oxides into multiple strips of X-direction first active areas, and the multiple strips of X-direction field oxides and the multiple strips of X-direction first active areas are arranged in parallel;
• an X direction is a direction parallel to a length direction of the X-direction first active areas, and a Y direction is perpendicular to the X direction;
• opening the first region to expose upper surfaces of the X-direction field oxides and upper surfaces of the X-direction first active areas in the first region;
• performing photolithography and etching to form a U-shaped trench in each X-direction first active area along a plurality of pairs of Y-direction openings, wherein each pair of Y-direction openings is composed of an adjacent two Y-direction openings along the X direction;
• and
• forming a trench oxide layer on the upper surfaces of the X-direction first active areas and surfaces of the U-shaped trenches;
• S2:
• depositing semi-floating gate polysilicon, wherein the U-shaped trenches are filled with the semi-floating gate polysilicon;
• S3:
• performing photolithography and etching to remove semi-floating gate polysilicon on the X-direction field oxides;
• S4:
• depositing a gate oxide layer;
• S5:
• depositing control gate polysilicon;
• S6:
• depositing an SIN hard mask;
• S7:
• performing photolithography and etching to remove the SIN hard mask and the control gate polysilicon outside a set width on an X-direction outer side of each pair of Y-direction openings, stop at the gate oxide layer, and reserve the SIN hard mask and the control gate polysilicon between each pair of Y-direction openings and within the set width on the X-direction outer side thereof;
• S8:
• depositing an SIN sidewall dielectric layer;
• S9:
• etching the SIN sidewall dielectric layer to remove the SIN sidewall dielectric layer above the control gate polysilicon corresponding to each pair of Y-direction openings, remove the SIN sidewall dielectric layer above the gate oxide layer on an X-direction outer side of the control gate polysilicon corresponding to each pair of Y-direction openings, and form a control gate sidewall;
• S10:
• performing self-aligned etching on the trench oxide layer by using the SIN hard mask and the control gate sidewall as a mask to remove the gate oxide layer, the semi-floating gate polysilicon, and the trench oxide layer on the X-direction outer side of the control gate polysilicon corresponding to each pair of Y-direction openings, and expose the X-direction outer side of the semi-floating gate polysilicon corresponding to each pair of Y-direction openings as a contact window;
• S11:
• growing a silicon epitaxy on the upper surfaces of exposed X-direction first active areas and at the contact window of the semi-floating gate polysilicon;
• and
• S12:
• performing subsequent processes.