US 2026/0190402 A1Published application

Semiconductor device including seed layer and method for manufacturing the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsTing-Hsiang CHANG, Shu Ling LIAO, Yu-Ru LIN, Sung-En LIN, Tze-Liang LEE

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Abstract

A method for manufacturing a semiconductor device includes: forming a stack structure on a substrate, the stack structure including sacrificial layer portions and channel layer portions which are alternately stacked; forming a trench that penetrates the stack structure and that terminates at an upper surface of the substrate; forming an insulator layer to cover the substrate and the stack structure; forming a seeding layer on the insulator layer; forming a protecting layer on the seeding layer; removing the protecting layer, an upper portion and an interconnecting portion of the seeding layer, and an upper portion and an interconnecting portion of the insulator layer; and forming a source/drain portion on a lower portion of the insulator layer and a lower portion of the seeding layer.

Claims20

Dependent claims

A method for manufacturing a semiconductor device, comprising:

forming a stack structure on a substrate, the stack structure including a plurality of sacrificial layer portions and a plurality of channel layer portions which are alternately stacked,
forming a trench that penetrates the stack structure and that terminates at an upper surface of the substrate;
forming an insulator layer to cover the substrate and the stack structure, the insulator layer including an upper portion disposed over an upper surface of the stack structure, a lower portion disposed over the substrate and in the trench, and an interconnecting portion interconnecting the upper portion and the lower portion and laterally covering the stack structure;
forming a seeding layer on the insulator layer, the seeding layer including an upper portion disposed on the upper portion of the insulator layer, a lower portion disposed on the lower portion of the insulator layer, and an interconnecting portion interconnecting the upper portion and the lower portion of the seeding layer and disposed on the interconnecting portion of the insulator layer;
forming a protecting layer on the seeding layer;
removing the protecting layer, the upper portion and the interconnecting portion of the seeding layer, and the upper portion and the interconnecting portion of the insulator layer;
and
forming a source/drain portion on the lower portion of the insulator layer and the lower portion of the seeding layer.

5 more elements

A method for manufacturing a semiconductor device, comprising:

forming two stack portions on a substrate, the two stack portions being spaced apart from each other and each of the two stack portions including a plurality of sacrificial features and a plurality of channel features which are alternately stacked;
forming an insulator layer to cover the substrate and the two stack portions, the insulator layer including an upper portion disposed over an upper surface of each of the two stack portions, a lower portion disposed on the substrate and between the two stack portions, and an interconnecting portion interconnecting the upper portion and the lower portion and laterally covering each of the two stack portions;
forming a seeding layer on the insulator layer, the seeding layer including an upper portion disposed on the upper portion of the insulator layer, a lower portion disposed on the lower portion of the insulator layer, and an interconnecting portion interconnecting the upper portion and the lower portion of the seeding layer and disposed on the interconnecting portion of the insulator layer;
forming a protecting layer on the seeding layer;
removing the protecting layer, the upper portion and the interconnecting portion of the seeding layer, and the upper portion and the interconnecting portion of the insulator layer;
and
forming a source/drain portion on the lower portion of the insulator layer and the lower portion of the seeding layer.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/002,260Filed 26 Dec 2024
Published: 2 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
H10D 30/014
Manufacture or treatment: of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron…
H10D 30/0196
Forming inner spacers between adjacent channels, e.g. changing their shapes or sizes: by modifying properties of the inner spacers
H10D 30/43
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having one-dimensional [1D] charge…