Semiconductor memory device
AssigneeSamsung Electronics Co., Ltd.
InventorsHyuncheol KIM, Yongseok KIM, Dongsoo WOO, Kyunghwan LEE, Minjun LEE
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Abstract
A semiconductor memory device may include a substrate, first and second impurity regions on the substrate, first and second gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.
Claims20
A semiconductor memory device, comprising:
- a substrate;
- a stack structure including interlayer dielectric layers and word lines, which are alternately and repeatedly stacked on the substrate, the word lines extending in a first direction parallel to a top surface of the substrate;
- semiconductor patterns crossing the word lines and extending in a second direction crossing the first direction;
- a ferroelectric pattern and a charge trap pattern interposed between each pair of the word lines and the semiconductor patterns;
- bit lines, which extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction, and each of which is in contact with first side surfaces of the semiconductor patterns spaced apart from each other in the third direction;
- and
- a source line, which is in contact with second side surfaces of the semiconductor patterns opposite to the first side surfaces,
- wherein each of the semiconductor patterns comprises:
- a first impurity region adjacent to each of the bit lines;
- a second impurity region adjacent to the source line;
- and
- a channel region between the first and second impurity regions,
- wherein the first and second impurity regions have different conductivity types from each other,
- wherein the charge trap pattern is in direct contact with the channel region of each of the semiconductor patterns, and
- wherein the ferroelectric pattern is formed of a ferroelectric material.
A semiconductor memory device, comprising:
- a first word line;
- a first semiconductor pattern overlapping the first word line;
- a first bit line electrically connected to the first semiconductor pattern and extending in a vertical direction;
- and
- a ferroelectric pattern and a charge trap pattern between the first word line and the first semiconductor pattern,
- wherein the ferroelectric pattern is disposed between the charge trap pattern and the first word line, and
- wherein the ferroelectric pattern is formed of a ferroelectric material.
A semiconductor memory device, comprising:
- a first word line;
- a second word line overlapping the first word line;
- a first semiconductor pattern penetrating the first word line;
- a second semiconductor pattern penetrating the second word line;
- a first bit line electrically connected to the first semiconductor pattern and the second semiconductor pattern;
- a first ferroelectric pattern and a first charge trap pattern between the first word line and the first semiconductor pattern;
- and
- a second ferroelectric pattern and a second charge trap pattern between the second word line and the second semiconductor pattern,
- wherein the first ferroelectric pattern and the second ferroelectric pattern are formed of a ferroelectric material.
Dependencies are inferred from the claim text.