US 2026/0190380 A1Published application

High-k/metal gate ldmos nanosheet device

OwnerDaniel Pham, Henry Litzmann Edwards +5inventors

InventorsDaniel Pham, Henry Litzmann Edwards, Sujatha Sampath, Ali Saadat, Orlando Lazaro, Vijay K. Reddy, Steven Kummerl

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Abstract

Disclosed examples include microelectronic devices, e.g., integrated circuits and methods of making such devices. One example includes a microelectronic device including a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor may include a high-k gate dielectric and a metal gate. The (LDMOS) transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region towards the drain region and field plate conductor layers that extend from the drain region towards the source region with gate dielectric layers and field relief dielectric layers separating the gate conductor layers from the field plate conductor layers.

Claims18

Dependent claims

A microelectronic device, comprising:

a first doped semiconductor region and a second doped semiconductor region extending into a semiconductor substrate, the first and second doped semiconductor regions having a first conductivity type and the semiconductor substrate having an opposite second conductivity type;
a semiconductor layer contacting the first doped semiconductor region and the second doped semiconductor region;
a first dielectric layer contacting the first doped semiconductor region;
a second dielectric layer contacting the second doped semiconductor region;
a first conductive layer contacting the first dielectric layer wherein the first dielectric layer separates the first conductive layer from the first doped semiconductor region;
a third dielectric layer separating the first conductive layer from the semiconductor layer;
a second conductive layer contacting the second dielectric layer wherein the second dielectric layer separates the second conductive layer from the second doped semiconductor region;
and
a fourth dielectric layer separating the second conductive layer from the semiconductor layer, wherein the second dielectric layer and the fourth dielectric layer are between the first conductive layer and the second conductive layer.

6 more elements

A method of forming a microelectronic device comprising:

forming a trench in a semiconductor substrate having a first conductivity type;
forming a semiconductor nanosheet stack in the trench including a semiconductor layer and a sacrificial layer;
forming a source trench in the semiconductor nanosheet stack and removing a portion of the sacrificial layer contacting the source trench and exposing a portion of the semiconductor layer nearest the source trench;
forming a third dielectric layer contacting the semiconductor layer,
forming a first conductive layer contacting the third dielectric layer;
forming a first dielectric layer between the first conductive layer and the source trench;
forming a first doped semiconductor region by filling the source trench with a first doped semiconductor of the first conductivity type, the first doped semiconductor being a source region;
forming a drain trench in the semiconductor nanosheet stack and removing the sacrificial layer contacting the drain trench exposing a portion of the semiconductor layer nearest the drain trench;
forming a fourth dielectric layer on the semiconductor layer;
forming a second conductive layer on the fourth dielectric layer;
forming a second dielectric layer between the second conductive layer and the drain trench;
and
forming a second doped semiconductor region by filling the drain trench with a second doped semiconductor of the first conductivity type, the second doped semiconductor being a drain region.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/003,730Filed 27 Dec 2024
Published: 2 Jul 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 30/0193
Forming stacked channels, e.g. changing their shapes or sizes: by modifying properties of the stacked channels
H10D 30/65
Double-diffused metal-oxide semiconductor [DMOS] FETs: lateral dmos [ldmos] fets
H10D 30/0191
Of FETs having stacked nanowire, nanosheet or nanoribbon channels: forming stacked channels, e.g. changing their shapes or sizes
H10D 30/0197
Forming inner spacers between adjacent channels, e.g. changing their shapes or sizes: the inner spacers having different properties