High-density low-k dielectric layer

A method, comprising:

• forming, over a substrate, a stack comprising a plurality of channel layers interleaved by a plurality of sacrificial layers;
• forming a fin-shaped structure from a portion of the substrate and the stack;
• forming a dummy gate stack over a channel region of the fin-shaped structure;
• after the forming of the dummy gate stack, depositing a gate spacer layer over the dummy gate stack and the substrate;
• forming a source/drain recess over a source/drain region of the fin-shaped structure;
• selectively and partially etching the plurality of sacrificial layers to form inner spacer recesses;
• depositing an inner spacer layer over the inner spacer recesses;
• anisotropically etching the inner spacer layer to form inner spacer features in the inner spacer recesses;
• forming a source/drain feature in the source/drain recess;
• removing the dummy gate stack;
• selectively removing the plurality of sacrificial layers in the channel region to release the plurality of channel layers as a plurality of channel members;
• and
• forming a gate structure to wrap around each of the plurality of channel members,
• wherein the depositing of the gate spacer layer comprises:
• depositing a first precursor over the dummy gate stack and the substrate,
• oxidizing the first precursor over the dummy gate stack and the substrate, and
• densifying the oxidized first precursor to form the gate spacer layer,
• wherein the first precursor comprises a disilacyclobutane backbone.

A semiconductor structure, comprising:

• a channel region over a substrate;
• a gate structure over the channel region and comprising a gate dielectric layer and a gate electrode over the gate dielectric layer;
• a source/drain feature interfacing the channel region;
• a source/drain contact over the source/drain feature;
• and
• a gate spacer disposed between the gate structure and the source/drain contact,
• wherein the gate spacer comprises disilacyclobutane functional groups.