Method of manufacturing semiconductor device and semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorTatsuo SHIMIZU
Life of this patent
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Abstract
A method of manufacturing a semiconductor device according to an embodiment includes: forming a mask material having an opening on a surface of a silicon carbide layer; forming a trench in the silicon carbide layer using the mask material as a mask; performing first ion implantation for implanting carbon (C) into a bottom face of the trench using the mask material as a mask; forming a sidewall material on a side face of the trench; performing second ion implantation for implanting a p-type first impurity into the bottom face of the trench using the sidewall material as a mask; and performing heat treatment at 1600° C. or more.
Claims20
A method of manufacturing a semiconductor device comprising:
- forming a mask material having an opening on a surface of a silicon carbide layer;
- forming a trench in the silicon carbide layer using the mask material as a mask;
- performing first ion implantation for implanting carbon (C) into a bottom face of the trench using the mask material as a mask;
- forming a sidewall material on a side face of the trench;
- performing second ion implantation for implanting a p-type first impurity into the bottom face of the trench using the sidewall material as a mask;
- and
- performing heat treatment at 1600° C. or more.
A method of manufacturing a semiconductor device comprising:
- forming a first mask material having an opening on a surface of a silicon carbide layer;
- forming a trench having a first side face and a second side face and extending in a first direction parallel to the surface in the silicon carbide layer using the first mask material as a mask;
- performing first ion implantation for implanting carbon (C) into the second side face of the trench using the first mask material as a mask;
- performing second ion implantation for implanting a p-type first impurity into the second side face of the trench using the first mask material as a mask;
- performing third ion implantation for implanting carbon (C) into a bottom face of the trench using the first mask material as a mask;
- forming a sidewall material on the first side face and the second side face of the trench;
- performing fourth ion implantation for implanting a p-type second impurity into the bottom face of the trench using the sidewall material as a mask;
- and
- performing heat treatment at 1600° C. or more.
A semiconductor device comprising:
- a silicon carbide layer having a first face parallel to a first direction and a second direction perpendicular to the first direction, and a second face parallel to the first face;
- a first trench disposed in the silicon carbide layer and extending in the first direction on the first face;
- a first gate electrode disposed in the first trench;
- a first gate insulating layer disposed between the first gate electrode and the silicon carbide layer;
- a second trench disposed in the silicon carbide layer, the second trench extending in the first direction on the first face, a first distance between the first trench and the second trench in the second direction being 1.0 μm or less;
- a second gate electrode disposed in the second trench;
- a second gate insulating layer disposed between the second gate electrode and the silicon carbide layer;
- an n-type first silicon carbide region disposed in the silicon carbide layer;
- a p-type second silicon carbide region disposed in the silicon carbide layer, disposed between the first silicon carbide region and the first face, and disposed between the first trench and the second trench;
- an n-type third silicon carbide region disposed in the silicon carbide layer and disposed between the second silicon carbide region and the first face;
- a p-type fourth silicon carbide region disposed in the silicon carbide layer, disposed between the first silicon carbide region and the first trench, and having a first p-type impurity concentration higher than 1×1020 cm−3;
- a p-type fifth silicon carbide region disposed in the silicon carbide layer, disposed between the first silicon carbide region and the second trench, and having a second p-type impurity concentration higher than 1×1020 cm−3;
- a first electrode disposed on a side of the first face with respect to the silicon carbide layer and electrically connected to the second silicon carbide region and the third silicon carbide region;
- and
- a second electrode disposed on a side of the second surface with respect to the silicon carbide layer,
- wherein a second distance in the second direction between the fourth silicon carbide region and the fifth silicon carbide region is ½ or more of the first distance.
Dependencies are inferred from the claim text.