Stacked embedded memory array with narrow logic-to-memory transition region

An apparatus, comprising:

• a logic region comprising one or more interconnect lines or vias extending through a first dielectric material over a device layer, wherein a border of the logic region comprises a first sidewall of the first dielectric material;
• a memory region over the device layer and laterally adjacent the logic region, the memory region comprising a second dielectric material and a stack of memory cells, the second dielectric material to both sides of the stack of memory cells, the second dielectric material comprising second and third sidewalls, the second sidewall on the stack of memory cells, the third sidewall adjacent the logic region, a conductor extending vertically through the memory cells, wherein a first of the memory cells are not vertically aligned with any of the one or more interconnect lines;
• and
• a transition region separating the logic and memory regions, the transition region comprising a third dielectric material between the first and second dielectric materials, the transition region having a width less than half of a height of the stack of memory cells, the width separating fourth and fifth sidewalls of the third dielectric material.

A method, comprising:

• depositing a first metallic layer and a first dielectric layer over a substrate, the first dielectric layer over the first metallic layer, the substrate comprising one or more interconnect layers over a device layer;
• forming an opening in the one or more interconnect layers, the opening adjacent one or more interconnect lines in the one or more interconnect layers;
• depositing a second metallic layer and a second dielectric layer conformally over first and second sidewalls of the opening, the second dielectric layer over a first portion of the second metallic layer on the first sidewall and a second portion of the second metallic layer on the second sidewall;
• exposing the first and second portions of the second metallic layer by removing the second dielectric layer;
• forming a stack of alternating third and fourth dielectric layers between the first and second portions of the second metallic layer;
• and
• replacing the first and second portions of the second metallic layer with a dielectric material.