Semiconductor structures and memory arrays
OwnerPeiching LING, Nanray WUinventors
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Abstract
The present disclosure relates to semiconductor structures, memory arrays, and manufacturing methods thereof. The semiconductor structure includes a first dielectric layer, a semiconductor layer, and a dual gate structure. The semiconductor layer is disposed over the first dielectric layer. The semiconductor layer includes a source region, a drain region, and a body region between the source region and the drain region. The dual gate structure is disposed over the body region. The dual gate structure includes a first gate, a second gate, and a spacing material. The second gate includes a first horizontal section laterally distanced from the first gate. The spacing material is disposed between the first gate and the first horizontal section of the second gate.
Claims60
A semiconductor structure, comprising:
- a first dielectric layer;
- a semiconductor layer over the first dielectric layer, the semiconductor layer comprising a source region, a drain region, and a body region between the source region and the drain region;
- and
- a dual gate structure over the body region;
- wherein the dual gate structure comprises:
- a first gate;
- a second gate comprising a first horizontal section laterally distanced from the first gate;
- and
- a spacing material between the first gate and the first horizontal section of the second gate.
A memory array, comprising:
- a first dielectric layer;
- a semiconductor layer over the first dielectric layer, and
- a first column of memory cell comprising a first memory cell and a second memory cell arranged in a first direction, wherein each of the first memory cell and the second memory cell comprises a source region in the semiconductor layer, a drain region in the semiconductor layer, a body region in the semiconductor layer between the source region and the drain region, and a first gate and a second gate over the body region, wherein the second gate of the first memory cell comprises a first horizontal section laterally distanced from the first gate of the first memory cell, the second gate of the second memory cell comprises a first horizontal section laterally distanced from the first gate of the second memory cell, and wherein the first gate of the first memory cell is electrically connected to the first gate of the second memory cell, and the second gate of the first memory cell is electrically connected to the second gate of the second memory cell.
A method for making a semiconductor structure, comprising:
- (a) receiving a first structure including a first substrate over a first dielectric layer;
- (b) defining an active area in the first substrate;
- (c) forming a dual gate structure over the active area, wherein the dual gate structure comprises a first gate, a second gate comprising a first horizontal section laterally distanced from the first gate, and a spacing material laterally between the first gate and the first horizontal section of the second gate;
- and
- (d) forming a source region and a drain region in the active area.
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Dependencies are inferred from the claim text.