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US 2026/0190316 A1Published application
Semiconductor-element-including memory device and method for manufacturing the same
AssigneeUnisantis Electronics Singapore Pte. Ltd.
InventorsNozomu HARADA, Koji SAKUI
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Abstract
A semiconductor-element-including memory device and a method for manufacturing the same are provided. Gate insulating layers in contact with respective both side surfaces of first and second channel semiconductor layers aligned in parallel as seen in plan view, drive gate conductor layers aligned in contact with the gate insulating layers, and electrostatic shielding conductor layers are provided. N+0 layers are provided on both ends of the first channel semiconductor layer, and N+ layers are provided on both ends of the second channel semiconductor layer.
Claims12
A semiconductor-element-including memory device, comprising:
- a first channel semiconductor layer and a second channel semiconductor layer that are apart from a substrate in a vertical direction and that extend in parallel in a horizontal direction;
- a first impurity region and a second impurity region in contact with both ends of the first channel semiconductor layer;
- a third impurity region and a fourth impurity region in contact with both ends of the second channel semiconductor layer;
- a first gate insulating layer in contact with a vertical side surface of the first channel semiconductor layer that is located on a side not facing the second channel semiconductor layer;
- a second gate insulating layer in contact with a vertical side surface of the first channel semiconductor layer facing the second channel semiconductor layer;
- a third gate insulating layer in contact with a vertical side surface of the second channel semiconductor layer facing the first channel semiconductor layer;
- a fourth gate insulating layer in contact with a vertical side surface of the second channel semiconductor layer that is located on a side not facing the first channel semiconductor layer;
- a first gate conductor layer or two first gate conductor layers in contact with the first gate insulating layer and a second gate conductor layer adjacent to the first gate conductor layer or the two first gate conductor layers;
- a third gate conductor layer or two third gate conductor layers in contact with the second gate insulating layer and a fourth gate conductor layer that is adjacent to the third gate conductor layer or the two third gate conductor layers and that is continuous from a surface of the second gate insulating layer to a surface of the third gate insulating layer;
- a fifth gate conductor layer or two fifth gate conductor layers that is or are in contact with the third gate insulating layer and that is or are adjacent to the fourth gate conductor layer;
- and
- a sixth gate conductor layer or two sixth gate conductor layers in contact with the fourth gate insulating layer and a seventh gate conductor layer adjacent to the sixth gate conductor layer or the two sixth gate conductor layers, wherein
- the first gate conductor layer or the two first gate conductor layers, the third gate conductor layer or the two third gate conductor layers, the fifth gate conductor layer or the two fifth gate conductor layers, and the sixth gate conductor layer or the two sixth gate conductor layers have an identical shape and are overlapped on one another as seen in vertical cross section, and
- the second gate conductor layer, the fourth gate conductor layer, and the seventh gate conductor layer have an identical shape and are overlapped on one another as seen in vertical cross section.
11 more elements
A method for manufacturing a semiconductor-element-including memory device, comprising:
- forming a first semiconductor layer and a second semiconductor layer that are apart from a substrate in a vertical direction, that extend in a horizontal direction in parallel to a first direction as seen in plan view, and that each have a first insulating layer thereon and thereunder in the vertical direction;
- forming a first gate insulating layer in contact with each of side surfaces of the first semiconductor layer and the first insulating layer that are located on the same side and each of side surfaces of the second semiconductor layer and the first insulating layer that are located on the same side;
- forming first gate conductor layers in contact with the first gate insulating layer;
- filling a space between the first gate conductor layers facing each other to form a second insulating layer;
- etching the first gate insulating layer, the first gate conductor layers, and the second insulating layer using a first mask material layer extending in a second direction orthogonal to the first direction as a mask as seen in plan view to form a first space on a side of one ends of the first semiconductor layer and the second semiconductor layer of the first mask material layer and to form a second space on a side of the other ends of the first semiconductor layer and the second semiconductor layer of the first mask material layer;
- forming a second gate insulating layer in contact with an inner side surface of the second space and a second gate conductor layer that entirely fills a third space surrounded by the second gate insulating layer;
- etching the first semiconductor layer and the second semiconductor layer located on a side of ends of the first gate conductor layer and the second gate conductor layer as seen in plan view to form a first channel semiconductor layer and a second channel semiconductor layer;
- and
- forming an impurity region containing a donor or acceptor impurity in high concentrations on both ends of the first channel semiconductor layer and the second channel semiconductor layer.
6 more elements
Dependencies are inferred from the claim text.