Synchronization Circuitry for Reducing Latency Associated with Image Passthrough

A computing system comprising:

• a content generation and delivery architecture including an image capture device, an image signal processing (ISP) pipeline, a partial frame buffer, a display pipeline, and a display device;
• synchronization circuitry;
• one or more processors;
• a non-transitory memory;
• and
• one or more programs stored in the non-transitory memory, which, when executed by the one or more processors, cause the computing system to:
• determine a temporal offset associated with the content generation and delivery architecture;
• obtain a first reference rate associated with a portion of the content generation and delivery architecture;
• generate, via the synchronization circuitry, a synchronization signal to adjust one or more clocks associated with the display pipeline or the display device based at least in part on the first reference rate;
• and
• operate the content generation and delivery architecture according to the synchronization signal and the temporal offset.

A non-transitory memory storing one or more programs, which, when executed by one or more processors of a computing system with synchronization circuitry and a content generation and delivery architecture including an image capture device, an image signal processing (ISP) pipeline, a partial frame buffer, a display pipeline, and a display device, cause the computing system to:

• determine a temporal offset associated with the content generation and delivery architecture;
• obtain a first reference rate associated with a portion of the content generation and delivery architecture;
• generate, via the synchronization circuitry, a synchronization signal to adjust one or more clocks associated with the display pipeline or the display device based at least in part on the first reference rate;
• and
• operate the content generation and delivery architecture according to the synchronization signal and the temporal offset.