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US 2026/0189400 A1Published application
Apparatus and method for an attack-resistant hardware accelerator
AssigneeIntel Corporation
InventorsSachin Taneja, Vikram Suresh, Raghavan Kumar, Joseph Friel, Avinash L. Varna, Sanu K. Mathew
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Abstract
Apparatus and method for an attack resistant hardware accelerator. For example, one embodiment comprises an attack-resistant masked HMAC-SHA-2 accelerator with: (a) multiplexer-based implementations of masked choose (Ch) logic and majority (Maj) logic with implicit masked-domain non-linear computations; (b) Secure Binary to arithmetic (BtoA) conversion logic integrated within a masked carry-save-adder gate; and (c) an area-efficient arithmetic-to-Binary (AtoB) mask conversion circuit using a secure masked sparse-tree adder.
Claims20
An integrated circuit (IC) for implementing hash-based message authentication code (HMAC) with secure hash operations, the IC comprising:
- a plurality of state registers to store a corresponding plurality of state words updated over multiple passes based on input message blocks;
- a permuted-congruential-generator (PCG) to generate a plurality of mask values to be combined with the plurality of state words to generate masked state words;
- transformation circuitry to perform linear and non-linear Boolean transformations on the masked state words, or subsets thereof, to generate transformed masked state values, the compression circuitry comprising sets of multiplexers operable as masked choose (Ch) and majority (Maj) selection circuits to perform the non-linear Boolean transformations;
- integrated Boolean-to-arithmetic (BtoA) and carry-save-adder (CSA) circuitry comprising secure BtoA conversion logic to perform Boolean-to-arithmetic conversions on the transformed masked state values to generate arithmetically masked state values and to perform a first set of additions using the arithmetically masked state values to generate first summed arithmetic values;
- adder circuitry to perform further sets of additions using the arithmetically masked state words and/or the first summed arithmetic values to generate second summed arithmetic values;
- and
- arithmetic-to-Boolean (AtoB) conversion circuitry comprising at least one masked sparse tree adder to subtract out arithmetic masks from the second summed arithmetic values to generate Boolean values to be used in a subsequent pass of the multiple passes.
4 more elements
A method for implementing hash-based message authentication codes (HMAC) with secure hash operations, comprising:
- storing a plurality of state words in a corresponding plurality of state registers, the plurality of state words to be updated over multiple passes based on input message blocks;
- generating, by a permuted-congruential-generator (PCG), a plurality of mask values to be combined with the plurality of state words to generate masked state words;
- performing, by transformation circuitry, linear and non-linear Boolean transformations on the masked state words, or subsets thereof, to generate transformed masked state values, wherein the non-linear Boolean transformation is performed by sets of multiplexers operable as masked choose (Ch) and majority (Maj) selection circuits;
- performing, by integrated Boolean-to-arithmetic (BtoA) and carry-save-adder (CSA) circuitry, Boolean-to-arithmetic conversions on the transformed masked state values to generate arithmetically masked state values and performing a first set of additions by the CSA circuitry using the arithmetically masked state values to generate first summed arithmetic values;
- performing further sets of additions using the arithmetically masked state words and/or the first summed arithmetic values to generate second summed arithmetic values;
- and
- subtracting out arithmetic masks, by arithmetic-to-Boolean (AtoB) conversion circuitry comprising at least one masked sparse tree adder, from the second summed arithmetic values to generate Boolean values to be used in a subsequent pass of the multiple passes.
4 more elements
A machine-readable medium having program code stored thereon which, when executed by an integrated circuit, causes the integrated circuit to perform operations, comprising:
- storing a plurality of state words in a corresponding plurality of state registers, the plurality of state words to be updated over multiple passes based on input message blocks;
- generating, by a permuted-congruential-generator (PCG), a plurality of mask values to be combined with the plurality of state words to generate masked state words;
- performing, by transformation circuitry, linear and non-linear Boolean transformations on the masked state words, or subsets thereof, to generate transformed masked state values, wherein the non-linear Boolean transformation is performed by sets of multiplexers operable as masked choose (Ch) and majority (Maj) selection circuits;
- performing, by integrated Boolean-to-arithmetic (BtoA) and carry-save-adder (CSA) circuitry, Boolean-to-arithmetic conversions on the transformed masked state values to generate arithmetically masked state values and performing a first set of additions by the CSA circuitry using the arithmetically masked state values to generate first summed arithmetic values;
- performing further sets of additions using the arithmetically masked state words and/or the first summed arithmetic values to generate second summed arithmetic values;
- and
- subtracting out arithmetic masks, by arithmetic-to-Boolean (AtoB) conversion circuitry comprising at least one masked sparse tree adder, from the second summed arithmetic values to generate Boolean values to be used in a subsequent pass of the multiple passes.
4 more elements
Dependencies are inferred from the claim text.