# US 2026/0189356 A1 · Synchronized two-way direct current (dc) data-bus-inversion encoding for simultaneous bi-directional signaling

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- Number: US 2026/0189356 A1
- Document ID: US20260189356A1
- Status: Published application
- Kind: A1
- Application number: 19/546,846
- Filed: 2026-02-23
- Published: 2026-07-02
- Earliest claimed: 2023-10-17
- Assignees: NVIDIA Corporation
- Applicants: NVIDIA Corporation
- Inventors: Ofek Abadi; Ido Yatzkar
- Web page: https://patentgrep.com/patent/US20260189356A1

## CPC

- H04L 5/1461: {Suppression of signals in the return path, i.e. bidirectional control circuits}
- H04L 7/042: {Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A communication system includes a plurality of simultaneous bidirectional (SBD) transceiver pairs coupled to a plurality of data lanes. An inversion SBD transceiver pair is coupled to a separate data lane. An encoder coupled to a first side of the plurality of SBD transceiver pairs, the encoder to generate data bus inversion (DBI)-encoded bits from a plurality of input bits and cause an inversion signal to be transmitted over the separate data lane. A decoder coupled to a second side of the plurality of SBD transceiver pairs, the decoder comprising a set of inversion circuits to receive the DBI-encoded bits and output decoded data based on the inversion signal received over the separate data lane.

## Claims

### Claim 1

A communication system comprising:
a plurality of simultaneous bidirectional (SBD) transceiver pairs coupled to a plurality of data lanes;
an inversion SBD transceiver pair coupled to a separate data lane;
an encoder coupled to a first side of the plurality of SBD transceiver pairs, the encoder to generate data bus inversion (DBI)-encoded bits from a plurality of input bits and cause an inversion signal to be transmitted over the separate data lane; and
a decoder coupled to a second side of the plurality of SBD transceiver pairs, the decoder comprising a set of inversion circuits to receive the DBI-encoded bits and output decoded data based on the inversion signal received over the separate data lane.

### Claim 2 (depends on 1)

The communication system of claim 1, wherein each inversion circuit of the set of inversion circuits comprises:
an inverter; and
a multiplexer controlled by the inversion signal.

### Claim 3 (depends on 1)

The communication system of claim 1, wherein the inversion signal indicates whether the encoder outputs unencoded bits or the DBI-encoded bits.

### Claim 4 (depends on 1)

The communication system of claim 1, wherein the DBI-encoded bits are based on direct current (DC)-DBI encoding that alternates between a first polarity where more zeros than ones are transmitted across the plurality of data lanes and a second polarity where more ones than zeros are transmitted across the plurality of data lanes, thereby DC-balancing transmission over the plurality of data lanes.

### Claim 5 (depends on 1)

The communication system of claim 1, wherein the encoder is further to cause a transmission signal comprising a specific bit pattern to be transmitted over the separate data lane before a start of DBI encoding.

### Claim 6 (depends on 1)

The communication system of claim 1, further comprising a second encoder coupled to the second side of the plurality of SBD transceiver pairs, wherein the second encoder is to, responsive to receipt of a transmission signal from the encoder over the separate data lane, initiate DBI encoding of a second plurality of bits to be transmitted over the plurality of data lanes.

### Claim 7 (depends on 1)

The communication system of claim 1, wherein the decoder at least one of:
is to output the decoded data synchronously with receipt of the inversion signal; or
comprises a buffer to synchronize output of the decoded data with a clock signal.

### Claim 8 (depends on 1)

The communication system of claim 1, further comprising:
a first integrated circuit (IC) chip comprising the encoder; and
a second IC chip comprising the decoder;
wherein at least one of the first IC chip and the second IC chip comprises one of a central processing unit (CPU), a graphics processing unit (GPU), or a data processing unit (DPU).

### Claim 9

A method of operating a communication system comprising a plurality of simultaneous bidirectional (SBD) transceiver pairs coupled to a plurality of data lanes, an inversion SBD transceiver pair coupled to a separate data lane, an encoder coupled to a first side of the plurality of SBD transceiver pairs, and a decoder coupled to a second side of the plurality of SBD transceiver pairs, the method comprising:
generating, by the encoder, data bus inversion (DBI)-encoded bits;
transmitting, by the encoder, an inversion signal over the separate data lane via the inversion SBD transceiver pair;
receiving, by the decoder, the DBI-encoded bits from the plurality of SBD transceiver pairs; and
inverting, by an inversion circuit of the decoder, a received DBI-encoded bit based on the inversion signal to generate decoded data.

### Claim 10 (depends on 9)

The method of claim 9, further comprising outputting, by the decoder, the decoded data, wherein the outputting comprises, for each inversion circuit of a set of inversion circuits of the decoder:
inverting a received DBI-encoded bit using an inverter; and
selecting, using a multiplexer controlled by the inversion signal, one of the received DBI-encoded bit or an output of the inverter.

### Claim 11 (depends on 9)

The method of claim 9, further comprising:
determining, by the encoder, that a plurality of bits to be transmitted comprise over fifty percent of a first binary value; and
generating, by the encoder, the DBI-encoded bits based on the determining.

### Claim 12 (depends on 9)

The method of claim 9, further comprising:
generating, by a clock divider circuit of the encoder, a DBI polarity signal by dividing a clock according to a division ratio;
alternating polarity of the DBI polarity signal; and
alternating DC-DBI encoding between a first polarity where more zeros than ones are transmitted and a second polarity where more ones than zeros are transmitted, thereby DC-balancing transmission over the plurality of data lanes.

### Claim 13 (depends on 9)

The method of claim 9, further comprising:
transmitting, by the encoder, a transmission signal comprising a specific bit pattern over the separate data lane before a start of DBI encoding;
detecting, by a pattern detector circuit of the encoder, the specific bit pattern; and
asserting, by the pattern detector circuit, an enable encoding signal that activates DBI encoding.

### Claim 14 (depends on 9)

The method of claim 9, further comprising:
receiving, by a second encoder coupled to the second side, a transmission signal from the encoder over the separate data lane;
generating, by the second encoder, a second DBI polarity signal that is synchronized to a first DBI polarity signal of the encoder based on detecting the transmission signal; and
generating, by the second encoder, a second plurality of DBI-encoded bits based on the second DBI polarity signal.

### Claim 15 (depends on 9)

The method of claim 9, further comprising:
for each inversion circuit of a set of inversion circuits of the encoder:
inverting a bit of unencoded data using an inverter; and
selecting, using a multiplexer based on a DBI flag, one of the bit of unencoded data or an inverted bit output by the inverter to generate a DBI-encoded bit.

### Claim 16

A decoder device for a simultaneous bidirectional (SBD) communication system, the decoder device comprising:
a set of inversion circuits coupled to receive data bus inversion (DBI)-encoded bits from a plurality of SBD transceiver pairs over a plurality of data lanes, each inversion circuit comprising an inverter and a multiplexer; and
an input terminal to receive an inversion signal from an inversion SBD transceiver pair over a separate data lane that is different than the plurality of data lanes;
wherein the set of inversion circuits is configured to output decoded data based on the inversion signal received from the inversion SBD transceiver pair.

### Claim 17 (depends on 16)

The decoder device of claim 16, wherein:
the inverter is to invert a received DBI-encoded bit; and
the multiplexer is controlled by the inversion signal to select one of the received DBI-encoded bit or an output of the inverter.

### Claim 18 (depends on 16)

The decoder device of claim 16, wherein the inversion signal indicates whether an encoder on an opposite side of the plurality of SBD transceiver pairs outputs unencoded bits or the DBI-encoded bits.

### Claim 19 (depends on 16)

The decoder device of claim 16, wherein the DBI-encoded bits are based on direct current (DC)-DBI encoding that alternates between a first polarity where more zeros than ones are transmitted across the plurality of data lanes and a second polarity where more ones than zeros are transmitted across the plurality of data lanes.

### Claim 20 (depends on 16)

The decoder device of claim 16, further comprising an encoder coupled to a same side of the plurality of SBD transceiver pairs as the decoder device, the encoder to, responsive to receipt of a transmission signal over the separate data lane, initiate DBI encoding of a plurality of bits to be transmitted over the plurality of data lanes.

### Claim 21 (depends on 20)

The decoder device of claim 20, wherein the encoder comprises:
a pattern detector circuit to detect a specific bit pattern within the transmission signal and assert an enable encoding signal that activates DBI encoding; and
a clock divider circuit to generate a DBI polarity signal that is synchronized to a DBI polarity signal of a second encoder positioned on an opposite side of the plurality of SBD transceiver pairs based on detecting the transmission signal.