Transistor assemblies with gate current shunting capability, and associated methods

A transistor assembly with gate current shunting capability, comprising:

• a first field effect transistor (FET) including a first gate, a first drain, and a first source, the first FET being an N-channel FET, and the first drain being electrically coupled to a first power supply;
• a first pull-down circuit element electrically coupled to the first gate;
• a first switching device electrically coupled in series with the first pull-down circuit element, the first switching device being configured to be controlled by a first control signal;
• a control circuit at least partially powered by a second power supply and configured to generate the first control signal to control an operating state of the first FET;
• and
• a capacitor and a second FET collectively configured to shunt current away from the first gate during a pre-power operating state of the transistor assembly, the pre-power operating state of the transistor assembly being characterized at least partially by (a) the first power supply being active and (b) the second power supply being inactive.