High-voltage drivers using low-voltage devices with protection circuitry for high endurance operation

An inverter, comprising:

• an input terminal, an output terminal, and first and second voltage terminals;
• a p-type metal-oxide-semiconductor (PMOS) MOS gate unit, the PMOS MOS gate unit including first, second and third PMOS transistors, each of the first, second and third PMOS transistors having a source, a drain and a gate, and configured to operate at a first operating voltage;
• and
• an n-type metal-oxide-semiconductor (NMOS) MOS gate unit, the NMOS MOS gate unit including first, second and third NMOS transistors, each of the first, second and third NMOS transistors having a source, a drain and a gate, and configured to operate at the first operating voltage;
• wherein:
• the first PMOS transistor has its source coupled to the first voltage terminal and its drain coupled to the source of the second PMOS transistor;
• the third PMOS transistor has its source coupled to the gate of the first PMOS transistor, its drain coupled to the input terminal, and its gate coupled to the gate of the second PMOS transistor;
• the drain of the second PMOS transistor is coupled to the output terminal;
• the first NMOS transistor has its source coupled to the second voltage terminal and its drain coupled to the source of the second NMOS transistor;
• the third NMOS transistor has its source coupled to the gate of the first NMOS transistor, its drain coupled to the input terminal, and its gate coupled to the gate of the second NMOS transistor;
• the drain of the second NPMOS transistor is coupled to the output terminal;
• and
• the inverter is operable at a second operating voltage significantly higher than the first operating voltage when a first limiting voltage significantly lower than the second operating voltage is applied to the gate of the third PMOS transistor and a second limiting voltage significantly lower than the second operating voltage is applied to the gate of the third NMOS transistor, the second operating voltage being applied across the first and second voltage terminals.

A metal-oxide-semiconductor (MOS) gate unit, comprising:

• a source terminal, a drain terminal, and a gate terminal;
• and
• first, second and third MOS transistors, each of the first, second and third MOS transistors having first and second current-carrying terminals and a control terminal, and configured to operate in a first operating voltage;
• wherein:
• the first MOS transistor has its first current-carrying terminal coupled to the source terminal of the MOS gate unit and its second current-carrying terminal coupled to the first current-carrying terminal of the second MOS transistor;
• the third MOS transistor has its first current-carrying terminal coupled to the control terminal of the first transistor, its second current-carrying terminal coupled to the gate terminal, and its control terminal coupled to the control terminal of the second transistor;
• the second current-carrying terminal of the second transistor is coupled to the drain terminal of the MOS gate unit;
• and
• the MOS gate unit is operable as a MOS transistor in a second operating voltage significantly higher than the first operating voltage when a limiting voltage significantly lower higher than the second operating voltage is applied to the control terminal of the third transistor.