Gate resistor bypass for rf fet switch stack

A switch circuit, comprising:

• a common node;
• a serial stack of switch transistors, wherein a gate for each of the switch transistors is coupled to the common node;
• a control node for a control signal to control each of the switch transistors;
• a first gate resistor coupled between the control node and the common node;
• and
• a first bypass switch coupled in parallel with the first gate resistor between the control node and the common node, wherein the first bypass switch includes an NMOS transistor and a PMOS transistor arranged in series.

A method for a switch circuit, comprising:

• charging a control signal from a negative voltage to a positive voltage to form a charged control signal;
• switching on a bypass switch for a first time duration in response to the charging of the first charged signal, wherein the bypass switch is coupled in parallel with a gate resistor and includes an NMOS transistor coupled in series with a PMOS transistor;
• and wherein switching on the bypass switch for the first time duration comprises switching on a PMOS transistor in series with a NMOS transistor, the NMOS transistor being already on prior to the switching on of the PMOS transistor;
• and
• coupling the charged control signal through the bypass switch during the first time duration to switch a serial stack of switch transistors from an off state to an on state.

A switch circuit, comprising:

• a serial stack of switch transistors;
• an input node for a control signal;
• a gate resistor coupled between a gate of each of the switch transistors and the input node;
• a bypass switch coupled in parallel with the gate resistor, wherein the bypass switch includes an NMOS transistor and a PMOS transistor;
• a first pulse generator configured to pulse a first pulsed signal to a first positive voltage for a first time duration in response to a rising edge of the control signal;
• a first level shifter configured to level shift the first pulsed signal from the first positive voltage to a second positive voltage for a portion of the first time duration, wherein the second positive voltage is greater than the first positive voltage;
• and
• a first network configured to couple the first pulsed signal from the first pulse generator and from the first level shifter to a gate of the NMOS transistor.