Flip-flop for reducing setup time
AssigneeSamsung Electronics Co., Ltd.
InventorsBomin JOO, Minji KIM, Taejung SEOL, Jaebeom YANG, Dalhee LEE
Life of this patent
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Abstract
A flip-flop includes a clock buffer that outputs, based on a clock signal, an inverted clock signal of the clock signal and a buffer clock signal obtained by delaying a phase of the clock signal, a master latch including a scan path and a data path, the data path receiving a data signal independently of the scan path, a slave latch that generates a first driving signal based on a first latch signal from the master latch and outputs an inverted output signal based on the first latch signal, the buffer clock signal, and the first driving signal, and an output driver that outputs an output signal based on the inverted output signal.
Claims20
A flip-flop comprising:
- a clock buffer configured to output, based on a clock signal, an inverted clock signal of the clock signal and a buffer clock signal obtained by delaying a phase of the clock signal;
- a master latch comprising a scan path and a data path, the data path being configured to receive a data signal independently of the scan path;
- a slave latch configured to generate a first driving signal based on a first latch signal from the master latch, the slave latch being configured to output an inverted output signal based on the first latch signal, the buffer clock signal, and the first driving signal;
- and
- an output driver configured to output an output signal based on the inverted output signal.
A flip-flop comprising:
- a clock buffer configured to output, based on a clock signal, an inverted clock signal of the clock signal, and a buffer clock signal obtained by delaying a phase of the clock signal;
- a master latch comprising a scan path and a data path, which are independent of each other, the master latch being configured to output a first latch signal having a second logic level that is lower than a first logic level for a data signal having the first logic level;
- a slave latch configured to generate a first driving signal having the first logic level based on the first latch signal, the slave latch being configured to output an inverted output signal having the second logic level in response to the first logic level of the first driving signal and a rising edge of the buffer clock signal;
- and
- an output driver configured to output an output signal having the first logic level based on the inverted output signal.
A flip-flop comprising:
- a clock buffer configured to output, based on a clock signal, an inverted clock signal of the clock signal, and a buffer clock signal obtained by delaying a phase of the clock signal;
- a master latch comprising a scan path and a data path, the scan path being configured to receive a scan enable signal and a scan input signal, and the data path being configured to receive a data signal independently of the scan path;
- a slave latch comprising a pull-up driver configured to pull up an inverted output signal based on a first latch signal of the master latch and the buffer clock signal, and a pull-down driver configured to pull down the inverted output signal based on the first latch signal and the inverted clock signal;
- and
- an output driver configured to output an output signal based on the inverted output signal.
Dependencies are inferred from the claim text.