Sub-channel support across same memory module
AssigneeAdvanced Micro Devices, Inc.
InventorsKedarnath Balakrishnan, Jean J. Chittilappilly, Jing Wang
Life of this patent
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Abstract
A memory controller system comprises a first memory controller for accessing a first sub-channel of a memory module, and a second memory controller for accessing a second sub-channel of the memory module. Each of the first and second memory controllers is configurable as one of a master memory controller and a slave memory controller. The master memory controller is enabled to send a global command to the memory module in response to a request, and the slave memory controller is disabled from sending the global command to the memory module in response to the request.
Claims20
A memory controller system, comprising:
- a first memory controller for accessing a first sub-channel of a memory module;
- and
- a second memory controller for accessing a second sub-channel of the memory module,
- wherein each of the first and second memory controllers is configurable as one of a master memory controller and a slave memory controller, wherein the master memory controller is enabled to send a global command to the memory module in response to a request, and the slave memory controller is disabled from sending the global command to the memory module in response to the request.
A memory controller comprising:
- a register for receiving and storing a master/slave signal;
- a control circuit operative to:
- enable the memory controller to send a global command to a memory interface queue to program a register clock driver of a memory module if the master/slave signal indicates the memory controller is a master memory controller;
- and
- prevent the memory controller from sending the global command to the memory interface queue to program the register clock driver of the memory module if the master/slave signal indicates the memory controller is a slave memory controller.
A method for accessing two channels of a memory module using first and second memory controllers, respectively, comprising:
- configuring a first one of the first memory controller and the second memory controller as a master memory controller;
- configuring a second one of the first memory controller and the second memory controller as a slave memory controller;
- receiving a request to change a state of the memory module;
- enabling the master memory controller to send a command in response to the request;
- and
- preventing the slave memory controller from sending the command in response to the request.
Dependencies are inferred from the claim text.