Memory device
AssigneeSK hynix Inc.
InventorChang Hyun KIM
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure relate to a memory device including at least one data line, a normal memory coupled to the data line and configured to output read data to the data line through a normal read operation during a cache load mode; a cache memory coupled to the data line and configured to write the read data as load data through a cache write operation during the cache load mode; and a controller configured to control the normal read operation of the normal memory and the cache write operation of the cache memory by generating and using a self-strobe signal and a self-column address signal during the cache load mode.
Claims17
A memory device comprising:
- a normal memory configured to perform a normal read operation or a normal write operation based on a first command signal, a first column address signal and a row address signal;
- a cache memory configured to perform a cache read operation or a cache write operation based on a second command signal and a second column address signal;
- a comparator configured to compare a previous row address signal with a current row address signal and generate a comparison signal corresponding to the comparison result;
- a handler configured to generate a load control signal, a self-strobe signal, a self-column address signal and the row address signal based on an active signal, a flag signal, the current row address signal and the comparison signal;
- and
- a control switch configured to generate the first command signal, the first column address signal, the second command signal and the second column address signal based on the load control signal, the self-strobe signal and the self-column address signal.
A memory device comprising:
- at least one data line;
- a normal memory coupled to the data line and configured to output read data to the data line through a normal read operation during a cache load mode;
- a cache memory coupled to the data line and configured to write the read data as load data through a cache write operation during the cache load mode;
- and
- a controller configured to control the normal read operation of the normal memory and the cache write operation of the cache memory by generating and using a self-strobe signal and a self-column address signal during the cache load mode.
A memory device comprising:
- a memory cell array;
- a cache memory;
- and
- a controller configured to:
- perform a normal read operation or a normal write operation on the memory cell array based on a first command signal, a first column address signal and a row address signal,
- perform a cache read operation or a cache write operation on the cache memory based on a second command signal and a second column address signal,
- during a cache mode, generate the first command signal and the first column address signal or the second command signal and the second column address signal, and
- during a precharge mode, generate the second command signal and the second column address signal, and then generate the first command signal and the first column address signal.
Dependencies are inferred from the claim text.