Asymmetric Clock Gating Scheme
AssigneeMicron Technology, Inc.
InventorBrynan Qiu
Life of this patent
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Abstract
A memory device includes command path circuitry and clock gating and generation circuitry. The command path circuitry includes shifting circuitry that may shift a command signal and that may include one or more final shifters. The clock gating and generation circuitry may generate a first set of phase-shifted clock signals, transmit the first set of phase shifted clock signals to the shifting circuitry, receive one or more busy signals from the shifting circuitry, determine, based on the one or more busy signals, that the one or more final shifters are storing the command signal, generate, based on the determination, a second set of phase-shifted clock signals.
Claims20
A memory device, comprising:
- command path circuitry comprising:
- shifting circuitry configured to shift a command signal, and comprising one or more final shifters, and
- clock gating and generation circuitry configured to:
- generate a first set of phase-shifted clock signals;
- transmit the first set of phase shifted clock signals to the shifting circuitry;
- receive one or more busy signals from the shifting circuitry;
- determine, based on the one or more busy signals, that the one or more final shifters are storing the command signal based on at least one of the first set of phase-shifted clock signals;
- and
- generate, based on the determination, a second set of phase-shifted clock signals.
A method, comprising:
- providing a first set of phase-shifted clock signals to command path circuitry of a memory device;
- receiving one or more busy signals from the command path circuitry;
- asserting, based on at least one of the one or more busy signals being asserted, an enable signal for a second set of phase-shifted clock signals;
- suppressing generation of the second set of phase-shifted clock signals based on the enable signal not being asserted;
- generating the second set of phase-shifted clock signals based on the enable signal being asserted;
- and
- transmitting the second set of phase-shifted clock signals to exit stage circuitry of the command path circuitry.
A memory device, comprising:
- first command path circuitry configured to shift a command signal based on a clock signal of a first set of clock signals;
- second command path circuitry configured to:
- receive the command signal from the first command path circuitry;
- shift the command signal based on a second set of clock signals;
- clock gating circuitry configured to:
- receive one or more busy signals from the first command path circuitry;
- generate an enable signal based on the one or more busy signals;
- clock generation circuitry configured to:
- receive the enable signal;
- and
- generate, based on the enable signal, the second set of clock signals.
Dependencies are inferred from the claim text.