On-package accelerator complex (ac) for integrating accelerator and ios for scalable ran and edge cloud solution

A multi-die package, comprising:

• a central processing unit (CPU) die having a plurality of cores and a plurality of caches and a first interconnect structure;
• a plurality of artificial intelligence (AI) accelerator dies, each AI accelerator die comprising a plurality of intellectual property (IP) blocks to execute workloads indicated by the plurality of cores;
• one or more high-bandwidth memory (HBM) stacks;
• and
• an interface die comprising:
• a second interconnect structure;
• a plurality of die-to-die interconnects to couple the second interconnect structure to the CPU die and the plurality of AI dies;
• a shared SRAM memory to be shared by the plurality of cores and the plurality of IP blocks;
• a memory controller to provide access by the cores and the plurality of IP blocks to the stacked HBM;
• one or more input-output (IO) interfaces coupled to the second interconnect structure, the one or more IO interfaces to couple the second interconnect structure to one or more IO devices;
• and
• data movement circuitry to offload data movement operations associated with the workloads in response to requests received over a data movement interface, the workloads associated with at least one of:
• the one or more IO devices, the plurality of IP blocks, and the cores;
• wherein the data movement circuitry is to cause data to be moved from a producer buffer associated with a producer IP block of the plurality of IP blocks to a consumer buffer associated with a consumer IP block of the plurality of IP blocks, the producer buffer and the consumer buffer allocated in one or more of:
• the HBM stacks, one or more external memory devices, and the shared SRAM memory.

A system, comprising:

• a plurality of multi-die packages;
• a plurality of inter-die interconnects to couple the plurality of multi-die packages, the multi-die packages comprising:
• a central processing unit (CPU) die having a plurality of cores and a plurality of caches and a first interconnect structure;
• a plurality of artificial intelligence (AI) accelerator dies, each AI accelerator die comprising a plurality of intellectual property (IP) blocks to execute workloads indicated by the plurality of cores;
• one or more high-bandwidth memory (HBM) stacks;
• and
• an interface die comprising:
• a second interconnect structure;
• a plurality of die-to-die interconnects to couple the second interconnect structure to the CPU die and the plurality of AI dies;
• a shared SRAM memory to be shared by the plurality of cores and the plurality of IP blocks;
• a memory controller to provide access by the cores and the plurality of IP blocks to the stacked HBM;
• one or more input-output (IO) interfaces coupled to the second interconnect structure, the one or more IO interfaces to couple the second interconnect structure to one or more IO devices;
• and
• data movement circuitry to offload data movement operations associated with the workloads in response to requests received over a data movement interface, the workloads associated with at least one of:
• the one or more IO devices, the plurality of IP blocks, and the cores;
• wherein the data movement circuitry is to cause data to be moved from a producer buffer associated with a producer IP block of the plurality of IP blocks to a consumer buffer associated with a consumer IP block of the plurality of IP blocks, the producer buffer and the consumer buffer allocated in one or more of:
• the HBM stacks, one or more external memory devices, and the shared SRAM memory.