Processor with non-standard sector size and operating method thereof

A processor, comprising a memory controller and a cache memory,

• wherein the memory controller:
• during a write operation to a main memory, stores A-byte sized data and B-byte sized metadata for the A-byte sized data through a single write command, and
• during a read operation from the main memory, reads the A-byte sized data and the B-byte sized metadata through a single read command, and transfers only the A-byte sized data from among the A-byte sized data and the B-byte sized metadata to the cache memory, and
• wherein the cache memory:
• receives the A-byte sized data from the memory controller or transmits the A-byte sized data to the memory controller, and
• includes at least one cache line that stores a plurality of the A-byte sized data.

A GPU (Graphics Processing Unit), comprising:

• a cache including at least one cache line that includes a plurality of cache sectors having a size of 2m-K bytes;
• a GDDR memory including a plurality of memory sectors having a size of 2m bytes;
• and
• a memory controller that controls the GDDR memory to store, during a write operation to the GDDR memory, first data of 2m-K byte size and first ECC redundancy of K-byte size corresponding to the first data in a first memory sector among the plurality of memory sectors.