System and method to use processor performance data to prove correct and intended execution of code and code pathways on an electronic device
OwnerJames Farley WARNEinventor
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Abstract
In an embodiment, a first compute device includes a memory and a first processor operatively coupled to the memory. The first processor is configured to send instrumented code to a second compute device that includes a second processor to cause the second processor to execute the instrumented code and generate performance data of the second processor. The instrumented code is generated based on un-instrumented code. The first processor is further configured to determine a status of the instrumented code based on the performance data, where the un-instrumented code has the status of the instrumented code.
Claims20
A non-transitory, processor-readable medium storing code that, when executed by a first processor of a first compute device, causes the first processor to:
- generate, based on first un-instrumented code, a map that represents a plurality of executions of a second processor included in a second compute device;
- instrument the first un-instrumented code to generate first instrumented code;
- send the first instrumented code and the map to the second compute device, the second processor configured to execute the plurality of executions based on the map to generate performance data associated with the second processor;
- receive the performance data associated with the second processor from the second compute device;
- generate a model based on the performance data associated with the second processor;
- send second instrumented code to a third compute device that includes a third processor configured to execute the second instrumented code and generate performance data associated with the third processor, the second instrumented code generated based on second un-instrumented code;
- and
- determine a status of the second instrumented code based on the model and the performance data associated with the third processor, the second un-instrumented code having the status of the second instrumented code.
A first compute device, comprising:
- a memory;
- and
- a first processor operatively coupled to the memory, the first processor configured to:
- send instrumented code to a second compute device that includes a second processor to cause the second processor to execute the instrumented code and generate performance data of the second processor, the instrumented code generated based on un-instrumented code;
- determine a status of the instrumented code based on the performance data, the un-instrumented code having the status of the instrumented code;
- detect an anomaly indicating that execution of the instrumented code is anomalous and does not match an intended or safe execution of at least one of the instrumented code or the un-instrumented code;
- and
- in response to detecting the anomaly, perform a remedial action at at least one of the instrumented code, the un-instrumented code, or the second compute device.
A method, comprising:
- receiving, via a processor of a first compute device, first code;
- generating, via the processor and based on the first code, a map that represents a plurality of executions of a second compute device;
- instrumenting, via the processor, the first code to generate instrumented code;
- sending, via the processor, the instrumented code and the map to the second compute device, the second compute device configured to execute the plurality of executions in response to receiving the instrumented code and based on the map to generate performance data;
- receiving, via the processor, the performance data from the second compute device;
- and
- generating, via the processor, a model based on the performance data, an anomaly at a third compute device detectable based on the model.
Dependencies are inferred from the claim text.