Method of manufacturing interconnect substrate

A method of manufacturing an interconnect substrate, comprising:

• providing a structure including a first interconnect layer, an electronic component having an electrode, and an insulating layer covering both the first interconnect layer and an electrode side of the electronic component;
• forming a first via hole penetrating the insulating layer and exposing an upper surface of the first interconnect layer;
• performing desmearing after forming the first via hole;
• forming, after the desmearing, a second via hole having an opening area smaller than that of the first via hole so as to penetrate the insulating layer and expose an upper surface of the electrode;
• performing anisotropic wet etching on the first interconnect layer exposed in the first via hole and the electrode exposed in the second via hole after forming the second via hole;
• and
• forming, by plating after the anisotropic wet etching, a second interconnect layer including an interconnect connected to the first interconnect layer via the first via hole and an interconnect connected to the electrode via the second via hole.