Method for producing interconnections
AssigneeCommissariat A L'energie Atomique Et Aux Energies Alternatives
InventorsThibaut CHÊNE, Fabrice NEMOUCHI, Roselyne SEGAUD, Thierry CHEVOLLEAU
Life of this patent
Estimating the term…
Abstract
A method of manufacturing an interconnecting level is disclosed. The method includes providing a substrate, forming a first metal layer, forming and patterning a dielectric etch-stop layer to define at least one line pattern with a via opening, forming a second metal layer over the patterned etch-stop layer, defining a via pattern aligned with the via opening, etching the second metal layer to form a via, and etching the first metal layer to form a line connected to the via through the via opening, thereby enabling aligned line-and-via formation using selective etching and a self-aligned dielectric stop.
Claims15
1-14. (canceled)
A method of manufacturing an interconnecting level comprising at least one line formed from a first metal material and at least one via formed from a second metal material, the method comprising:
- providing a substrate;
- forming a first metal layer on the substrate, the first metal layer comprising the first metal material;
- forming an etch-stop layer on the first metal layer, the etch-stop layer comprising a dielectric material having a selectivity to etching with respect to the first metal material;
- patterning the etch-stop layer through at least one first mask such that the patterned etch-stop layer defines at least one line pattern comprising at least one via opening;
- forming a second metal layer on the patterned etch-stop layer, the second metal layer comprising the second metal material;
- forming a second mask on the second metal layer defining at least one via pattern in vertical alignment with the at least one via opening;
- etching the second metal layer to form the at least one via beneath the second mask;
- and
- etching the first metal layer to form the at least one line beneath the at least one line pattern of the patterned etch-stop layer, the at least one line being connected to the at least one via through the at least one via opening.
An interconnect device comprising, in a vertical stack along a z-direction:
- a substrate;
- and
- an interconnecting level comprising:
- at least one connecting line comprising a first metal material;
- an etch-stop layer comprising a second dielectric material having a selectivity to etching with respect to the first metal material;
- and
- at least one connecting via comprising a second metal material;
- wherein the etch-stop layer includes at least one line pattern comprising at least one via opening configured to connect the at least one connecting via to the at least one connecting line, and
- wherein the etch-stop layer covers the at least one connecting line along the z-direction without extending outside the at least one connecting line when projected along the z-direction.
Dependencies are inferred from the claim text.