Fabrication of gate-all-around integrated circuit structures having gate dielectrics with differentiated transition layer thickness

An integrated circuit structure, comprising:

• a first fin;
• a second fin;
• a first gate stack over the first fin, wherein the first gate stack is an NMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a layer comprising silicon and oxygen and having a first thickness;
• and
• a second gate stack over the second fin, wherein the second gate stack is a PMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a layer comprising silicon and oxygen and having a second thickness greater than the first thickness.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of horizontal nanowires or fin;
• a second vertical arrangement of horizontal nanowires or fin;
• a first gate stack over the first vertical arrangement of horizontal nanowires or fin, wherein the first gate stack is an NMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a layer comprising silicon and oxygen and having a first thickness;
• and
• a second gate stack over the second vertical arrangement of horizontal nanowires or fin, wherein the second gate stack is a PMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a layer comprising silicon and oxygen and having a second thickness greater than the first thickness.