Vertical fin-based field effect transistor (finfet) with varying conductivity regions

A semiconductor device, comprising:

• a substrate characterized by a first conductivity type;
• a first active fin array comprising first active fins comprising a first number of fins and characterized by the first conductivity type;
• a second active fin array comprising second active fins and a second number of fins and characterized by the first conductivity type;
• a first inactive fin array comprising first inactive fins and interposed between the first active fin array and the second active fin array, wherein the first inactive fins are characterized by a reduced electrical conductivity compared to an electrical conductivity of the first active fins and the second active fins;
• an active gate region surrounding the first active fin array, the second active fin array, and the first inactive fin array and characterized by a second conductivity type opposite to the first conductivity type;
• a first source pad conductor coupled to the first active fins;
• and
• a second source pad conductor coupled to the second active fins;
• wherein:
• the first active fin array is configured as an active vertical FET;
• the second active fin array is configured as a sense FET;
• the second number of fins is less than the first number of fins;
• and
• the substrate, the first active fins, the second active fins, the first inactive fins, and the active gate region comprise III-nitride semiconductor material.

A method of fabricating a semiconductor device, comprising:

• providing a first active fin array comprising first active fins and a first number of fins;
• providing a second active fin array comprising second active fins and a second number of fins;
• providing a first inactive fin array comprising first inactive fins and interposed between the first active fin array and the second active fin array, wherein the first inactive fins are characterized by a reduced electrical conductivity compared to an electrical conductivity of the first active fins and the second active fins;
• providing an active gate region surrounding the first active fin array, the second active fin array, and the first inactive fin array;
• providing a first source pad conductor coupled to the first active fins;
• and
• providing a second source pad conductor coupled to the second active fins;
• wherein:
• the first active fin array is configured as an active vertical FET;
• the second active fin array is configured as a sense FET;
• and
• the second number of fins is less than the first number of fins.