US 2026/0181994 A1 · MULTI-LAYER ELECTRODE TO IMPROVE PERFORMANCE OF FERROELECTRIC MEMORY DEVICE

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a first interconnect in a first dielectric layer. A second dielectric layer overlies the first dielectric layer. A memory cell overlies the first interconnect and is at least partially in the second dielectric layer. The memory cell includes a first electrode, a second electrode, and a ferroelectric layer between the first and second electrodes. The first electrode includes a first conductive layer and a second conductive layer. The second electrode includes a third conductive layer and a fourth conductive layer. The third conductive layer is between the fourth conductive layer and the ferroelectric layer. The third conductive layer includes a middle region over the first interconnect and a peripheral region over an upper surface of the second dielectric layer. A lower surface of the middle region is vertically below the upper surface of the second dielectric layer.

Claims20

Dependent claims

An integrated chip, comprising:

a first interconnect in a first dielectric layer over a substrate;
a second dielectric layer over the first dielectric layer;
and
a memory cell over the first interconnect and at least partially in the second dielectric layer, wherein the memory cell comprises a first electrode, a second electrode, and a ferroelectric layer between the first and second electrodes, wherein the first electrode comprises a first conductive layer and a second conductive layer between the first conductive layer and the ferroelectric layer, wherein the second electrode comprises a third conductive layer and a fourth conductive layer, wherein the third conductive layer is between the fourth conductive layer and the ferroelectric layer, wherein the third conductive layer comprises a middle region over the first interconnect and a peripheral region over an upper surface of the second dielectric layer, wherein a lower surface of the middle region is vertically below the upper surface of the second dielectric layer.

1 more element

Dependencies are inferred from the claim text.

Multi-layer electrode to improve performance of ferroelectric memory device

Life of this patent

Multi-layer electrode to improve performance of ferroelectric memory device

Life of this patent

Abstract

Claims20