Semiconductor device

A semiconductor device comprising:

• a substrate including a first surface and a second surface opposing each other;
• an epitaxial layer positioned on the first surface of the substrate, including a gate trench, and having a first conductivity type;
• a gate electrode positioned within the gate trench;
• a gate insulating layer positioned between the epitaxial layer and the gate electrode;
• a source electrode positioned on the epitaxial layer;
• a well region positioned on a first side of the gate electrode, between the epitaxial layer and the source electrode, the well region having a second conductivity type, different from the first conductivity type;
• a first deep well region positioned on a second side of the gate electrode opposite the first side, and between the epitaxial layer and the source electrode, the first deep well region having the second conductivity type;
• a second deep well region positioned between the epitaxial layer and the source electrode, located on a first side of the well region, the second deep well region having the second conductivity type;
• a first doped layer positioned between the well region and the source electrode, the first doped layer having the first conductivity type;
• a second doped layer positioned between the first deep well region and the source electrode, the second doped layer having the second conductivity type;
• a third doped layer positioned between the second deep well region and the source electrode;
• a shield pattern positioned between the epitaxial layer and the first deep well region, the shield pattern having the second conductivity type;
• and
• a drain electrode positioned on the second surface of the substrate;
• wherein a width of the shield pattern is greater than or equal to a width of the first deep well region, and
• the shield pattern has a doping concentration greater than or equal to a doping concentration of the first deep well region.

A semiconductor device comprising:

• a substrate including an active area where a plurality of cells are positioned and a peripheral area surrounding at least a portion of the active area;
• and
• a gate frame positioned in the peripheral area, including a first portion and a second portion, the first portion and the second portion extending in a first direction and arranged spaced apart in a second direction intersecting the first direction,
• wherein the plurality of cells are positioned between the first portion and the second portion of the gate frame,
• wherein each of the plurality of cells includes:
• an epitaxial layer including a gate trench positioned on a first surface of the substrate and extending in the second direction, the epitaxial layer having a first conductivity type;
• a gate electrode positioned within the gate trench and electrically connected to the gate frame;
• a gate insulating layer positioned between the epitaxial layer and the gate electrode;
• a source electrode positioned on the epitaxial layer;
• a well region positioned on a first side of the gate electrode along the first direction, and positioned between the epitaxial layer and the source electrode, the well region having a second conductivity type different from the first conductivity type;
• a first deep well region positioned on a second side of the gate electrode opposite the first side along the first direction, and positioned between the epitaxial layer and the source electrode, the first deep well region having the second conductivity type;
• a shield pattern positioned between the epitaxial layer and the first deep well region, extending in the second direction, and overlapping the gate electrode;
• and
• a drain electrode positioned on a second surface of the substrate opposite the first surface,
• wherein a lower surface of the shield pattern includes a convex curved surface that is convex toward the drain electrode.