Memory cell
AssigneeFloadia Corporation
InventorsShinji YOSHIDA, Yasuhiko KAWASHIMA, Satoshi NODA, Takashi YAMAKI, Shuichi SATO, Toshikazu MATSUI, Yasuhiro TANIGUCHI, Kosuke OKUYAMA
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Abstract
A memory cell is capable of reliably injecting charges into a floating gate even when a film thickness of a gate insulating film is increased. The memory cell has a configuration in which a program transistor is constituted by a PMOS transistor, and electrons can be injected into a floating gate FG by hot electron injection using CHE. Accordingly, in the memory cell, even when film thicknesses of the gate insulating films are increased, the charges can be reliably injected into the floating gate FG.
Claims16
A memory cell of a nonvolatile semiconductor memory device, the memory cell comprising:
- a program transistor;
- and
- a read transistor, wherein
- the program transistor is formed in an N-type well, and includes a drain which is a P-type diffusion layer formed in a surface of the N-type well, a source which is a P-type diffusion layer formed in the surface of the N-type well and separated from the drain, a gate insulating film provided on the N-type well between the drain and the source, and a floating gate provided on the gate insulating film,
- the read transistor is formed in an N-type well, and includes a drain which is a P-type diffusion layer formed in a surface of the N-type well, a source which is a P-type diffusion layer formed in the surface of the N-type well and separated from the drain, a gate insulating film provided on the N-type well between the drain and the source, and a floating gate provided on the gate insulating film, and
- the floating gate of the program transistor and the floating gate of the read transistor are electrically connected to each other.
Dependencies are inferred from the claim text.