Retimer training and status state machine synchronization across multiple integrated circuit dies

An apparatus comprising:

• a plurality of circuit dies for retiming serial data links from a root complex to an endpoint;
• a plurality of data lanes distributed across the plurality of circuit dies that form a PCIe data link, each data lane comprising a respective upstream and downstream retimer training status and state machines (RTSSMs);
• a die-to-die RTSSM sync channel connected between each circuit die configured to carry a multi-bit lane status signal, the multi-bit lane status signal comprising aggregate RTSSM status information for each circuit die that collectively forms complete multi-die RTSSM status information;
• a state synchronization pipeline (SSP) in each circuit die, the SSP in a given circuit die configured to receive the multi-bit lane status signal and to accrue the complete RTSSM status information by incrementally storing the aggregate RTSSM status information from the remaining circuit dies, the SSP further configured to output RTSSM status information pertaining to the given circuit die onto the D2D RTSSM sync channel;
• and
• the respective upstream and downstream RTSSMs in each circuit die configured to analyze the aggregate RTSSM status information of the plurality of circuit dies upon synchronous accrual of the complete multi-die RTSSM status information, and to synchronously execute a state change in the circuit die.