Multiply-accumulate (mac) apparatus for in-memory computing

An apparatus, comprising

• a bit-cell array configured to generate an analog output corresponding to a multiply-accumulate (MAC) operation result using a multibit weight and a multibit input in charge domain, wherein the bitcell array comprises a plurality of bitcells connected to corresponding column bitlines via capacitive coupling, and wherein each column bitline is connected to a capacitor ladder to produce an analog output voltage that represents a combined MAC operation result of all column bitlines,
• a dual-mode activation module which is selectively operable either in a Deep Neural Network (DNN) mode and a Spiking Neural Network (SNN) mode, comprising
• a sample-and-hold circuit configured to sample the analog output voltage received from the capacitor ladder to an input and hold the analog output voltage sample at an output, the sample and hold circuit comprising a first reconfigurable capacitor bank, a second reconfigurable capacitor bank, and control switch elements for selectively coupling the first reconfigurable capacitor bank and the second reconfigurable capacitor bank to the input or the output,
• a comparator having a first input to receive the analog output voltage sample, a second input, and a control output,
• a digital-to-analog converter (DAC) having a digital control input and an analog voltage output connected to the second input of the comparator, and
• a control circuitry configured to receive a comparison result from the control output of the comparator and configured to control the dual-mode activation module in accordance with the selected one of the DNN mode and the SNN mode.