Level shifting circuit operating method
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., Tsmc China Company Limited
InventorsYaqi MA, Lei PAN, JunKui HU
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Abstract
A method of operating a level shifting circuit includes receiving, at a bias circuit, a first voltage level and a second voltage level, generating, from the bias circuit, a bias voltage having the greater of the first voltage level or the second voltage level, receiving the first voltage level at a source/drain (S/D) terminal of a first PMOS transistor included in a level shifter, receiving the second voltage level at a S/D terminal of a second PMOS transistor included in the level shifter, and receiving the bias voltage at a bulk terminal of each of the first PMOS transistor and the second PMOS transistor.
Claims20
A method of operating a level shifting circuit, the method comprising:
- receiving, at a bias circuit, a first voltage level and a second voltage level;
- generating, from the bias circuit, a bias voltage having the greater of the first voltage level or the second voltage level;
- receiving the first voltage level at a source/drain (S/D) terminal of a first PMOS transistor included in a level shifter;
- receiving the second voltage level at a S/D terminal of a second PMOS transistor included in the level shifter;
- and
- receiving the bias voltage at a bulk terminal of each of the first PMOS transistor and the second PMOS transistor.
A method of operating a level shifting circuit, the method comprising:
- receiving a first voltage level at a source/drain (S/D) terminal of a first PMOS transistor included in a bias circuit;
- receiving a second voltage level at a S/D terminal of a second PMOS transistor included in the bias circuit;
- generating, from the bias circuit, a bias voltage having the greater of the first voltage level or the second voltage level;
- receiving the first voltage level at a S/D terminal of a third PMOS transistor included in a level shifter;
- receiving the second voltage level at a S/D terminal of a fourth PMOS transistor included in the level shifter;
- and
- receiving the bias voltage at a bulk terminal of each of the first through fourth PMOS transistors.
A method of operating a level shifting circuit, the method comprising:
- receiving, at a bias circuit, a first voltage level and a second voltage level;
- generating, from the bias circuit, a bias voltage having the greater of the first voltage level or the second voltage level;
- receiving the first voltage level at a source/drain (S/D) terminal of a first PMOS transistor included in a level shifter;
- receiving the second voltage level at a S/D terminal of each of a second PMOS transistor included in the level shifter and a third PMOS transistor included in the level shifter;
- and
- receiving the bias voltage at a bulk terminal of each of the first through third PMOS transistors.
Dependencies are inferred from the claim text.