Semiconductor Device And Operation Method Of The Semiconductor Device

A method for operating a semiconductor device comprising:

• a power management unit, a signal adjustment portion, and a register group comprising a plurality of registers,
• wherein the signal adjustment portion comprises a buffer circuit, a first transistor, and a second transistor, and
• wherein each of the plurality of registers comprises a scan flip-flop and a storage circuit,
• the method for operating the semiconductor device comprising:
• a first step of turning on the first transistor and stating power supply to the buffer circuit;
• a second step of outputting a first signal to the register group by the power management unit through the buffer circuit and saving, in the storage circuit, data retained in the scan flip-flop in each of the plurality of registers;
• a third step of turning on the second transistor and supplying a second signal that is a low-potential level, in each of the plurality of registers included in the register group, to the storage circuit;
• and
• a fourth step of turning off the first transistor and stopping power supply to the buffer circuit.

A method for operating a semiconductor device comprising:

• a power management unit, a signal adjustment portion, and a register group comprising a plurality of registers,
• wherein the signal adjustment portion comprises a buffer circuit, a first transistor, and a second transistor, and
• wherein each of the plurality of registers comprises a scan flip-flop and a storage circuit,
• the method for operating the semiconductor device comprising:
• a first step of turning on the first transistor and starting power supply to the buffer circuit;
• a second step of outputting a first signal to the register group by the power management unit through the buffer circuit and saving, in the storage circuit, data retained in the scan flip-flop in each of the plurality of registers included in the register group;
• a third step of turning on the second transistor and supplying a second signal that is a low-potential level, in each of the plurality of registers included in the register group, to the storage circuit;
• a fourth step of turning off the first transistor and stopping power supply to the buffer circuit;
• a fifth step of turning on the first transistor and starting power supply to the buffer circuit;
• a sixth step of turning off the second transistor;
• a seventh step of outputting a third signal to the register group by the power management unit through the buffer circuit and reading out the data saved in the storage circuit to the scan flip-flop in each of the plurality of registers included in the register group;
• and
• an eighth step of turning off the first transistor and stopping power supply to the buffer circuit.

A semiconductor device comprising:

• a first layer and a second layer stacked over the first layer,
• wherein the first layer comprises a functional circuit comprising a first region, a first wiring comprising a region extending in a first direction, and a second wiring comprising a region extending in the first direction,
• wherein the functional circuit comprises a first transistor and a second transistor each comprising silicon in a semiconductor layer and a third wiring,
• wherein the first region is between the first wiring and the second wiring in a top view,
• wherein the first transistor comprises a first channel formation region and a first low-resistance region functioning as one of a source and a drain,
• wherein the second transistor comprises a second channel formation region,
• wherein the first low-resistance region overlaps with the third wiring,
• wherein one or more of the first channel formation region and the second channel formation region are in the first region,
• wherein the second layer comprises a storage circuit,
• wherein the storage circuit comprises a third transistor comprising an oxide semiconductor in a semiconductor layer,
• wherein the first layer or the second layer comprises a fourth transistor,
• wherein a gate of the first transistor is electrically connected to a gate of the second transistor,
• wherein the one of the source and the drain of the first transistor is electrically connected to the third wiring,
• wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
• wherein the other of the source and the drain of the first transistor, the other of the source and the drain of the second transistor, and a gate of the third transistor are electrically connected to one another,
• wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring, and
• wherein a first high power supply potential is supplied to the first wiring, a low power supply potential is supplied to the second wiring, and a second high power supply potential higher than the first high power supply potential is supplied to the other of the source and the drain of the fourth transistor.