Transposed Digital Filter Circuitry

Hybrid transposed finite impulse response (FIR) filter circuitry comprising:

• a first direct multi-tap FIR filter circuit to produce a first interim result;
• output delay circuitry to delay the first interim result based on a number of taps in the first direct multi-tap FIR filter to produce a delayed first interim result;
• a second direct multi-tap FIR filter circuit to produce a second interim result;
• and
• addition circuitry to add the delayed first interim result to the second interim result to produce a hybrid transposed FIR filter result.

An article of manufacture comprising one or more tangible, non-transitory, machine-readable media that, when executed by a data processing system, generates a system design for a programmable logic device that comprises a configuration of an embedded digital signal processing (DSP) block comprising:

• a first hardened multiplier circuit of the DSP block configured to multiply a first coefficient and a stream of input data to produce a first product;
• a second hardened multiplier circuit of the DSP block configured to multiply a second coefficient and the stream of input data to produce a second product;
• and
• one or more registers of the DSP block configured to provide delay to enable the DSP block to implement a transposed finite impulse response (FIR) filter.