Driving circuit and vertical cavity surface emitting laser system

A driving circuit, comprising a bias current control sub-circuit and an output driving sub-circuit, wherein

• an input end of the bias current control sub-circuit is connected to a power supply, and an output end of the bias current control sub-circuit is connected to an output end of the output driving sub-circuit and a driven element;
• the output driving sub-circuit comprises a differential pair module circuit, and the differential pair module circuit comprises a load resistor RL1, a load resistor RL2, a second current source, a transistor Q1, and a transistor Q2;
• a PMOS transistor is disposed between a power supply of the differential pair module circuit and the load resistor RL1 and the load resistor RL2;
• a source of the PMOS transistor is connected to the power supply of the differential pair module circuit, and a drain of the PMOS transistor is connected to the load resistor RL1 and the load resistor RL2 to form an intersection point;
• one end of the second current source is grounded, and one end of the second current source away from a ground direction is connected to both an emitter of the transistor Q1 and an emitter of the transistor Q2;
• and a collector of the transistor Q1 is connected to one end of the load resistor RL1 away from the PMOS transistor, and a collector of the transistor Q2 is connected to one end of the load resistor RL2 away from the PMOS transistor;
• a transistor Q3 is disposed between the transistor Q1 and the load resistor RL1, and a transistor Q4 is disposed between the transistor Q2 and the load resistor RL2;
• a collector of the transistor Q3 is connected to one end of the load resistor RL1 away from the PMOS transistor, an emitter of the transistor Q3 is connected to the collector of the transistor Q1, and a base of the transistor Q3 is connected to a voltage VB;
• and a collector of the transistor Q4 is connected to one end of the load resistor RL2 away from the PMOS transistor, an emitter of the transistor Q4 is connected to the collector of the transistor Q2, and a base of the transistor Q4 is connected to the voltage VB;
• one end of the load resistor RL2 close to the driven element is the output end of the output driving sub-circuit, one end of the load resistor RL2 close to the driven element is further connected to one end of a load resistor Rf, and one end of the load resistor Rf away from the load resistor RL2 is connected to a first input end of a first operational amplifier;
• one end of the load resistor RL1 close to the PMOS transistor is further connected to one end of a load resistor Rref, one end of the load resistor Rref away from the load resistor RL1 is connected to a second input end of the first operational amplifier, and one end of the load resistor Rref away from the load resistor RL1 is connected to a first current source;
• and
• an output end of the first operational amplifier is connected to a gate of the PMOS transistor.