Memory with Enhanced Design-for-Test Bypass Mode

A method of operation for a memory, comprising:

• processing a read data signal through a first logic gate in a read data latch to provide a latched output signal at an output terminal of the first logic gate responsive to a first binary value of a bypass signal during a read operation to the memory;
• latching a data in signal from a scan chain in a write data latch during a design-for-test bypass mode for the memory to provide a write data signal;
• and
• latching the write data signal in the read data latch responsive to a second binary value of the bypass signal during the design-for-test bypass mode for the memory.

A memory, comprising:

• a write data latch;
• a read data latch including a first logic gate having an input terminal for receiving a read data signal and having an output terminal for providing an output signal from the read data latch;
• and
• a second logic gate configured to process a write data signal from the write data latch with a bypass signal for a design-for-test bypass mode for the memory, wherein the read data latch includes a third logic gate including an input terminal coupled to an output terminal of the second logic gate.