Loading patent…
AssigneeMicron Technology, Inc.
InventorsLawrence Celso Miranda, Tomoko Ogura Iwasaki, Sheyang Ning, Jeffrey S. McNeil
Estimating the term…
Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and two or more target bitlines; classifying the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a programing voltage to be applied to the target wordline.
A system, comprising:
A system, comprising:
A system, comprising:
Dependencies are inferred from the claim text.