Resistive memory with enhanced redundancy writing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
Life of this patent
Estimating the term…
Abstract
A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuity configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.
Claims21
1-20. (canceled)
A memory device, comprising:
- a main memory array comprising main memory cells;
- and
- write circuity configured to perform a first programming operation on a main memory cell and to detect whether current of the main memory cell exceeds a predefined current threshold during the first programming operation.
Write circuitry for a memory device, comprising:
- a comparator having a first input terminal configured to receive a reference voltage signal, a second input terminal configured to receive a drive voltage signal, and an output terminal;
- a drive transistor having a first gate terminal connected to the output terminal and configured, in a first programming operation, to output a memory cell current to a memory cell of a first memory cell array and feedback the drive voltage signal to the second input terminal;
- and
- a reference transistor having a second gate terminal connected to the output terminal and configured to output an indicator signal at an indicator node that is connected to a current source configured to generate a reference current,
- wherein the indicator node is configured to output an indicator signal based on a comparison of the memory cell current and the reference current.
A method of writing a memory, comprising:
- performing a first set operation on a main memory cell of a main memory array;
- detecting whether current of the main memory cell exceeds a predefined current threshold during the first set operation;
- and
- disabling a second set operation if the current of the main memory cell exceeds the predefined current threshold during the first set operation.
Dependencies are inferred from the claim text.