Processor and method with accelerator access control

A processor comprising:

• an accelerator comprising an in-memory computing (IMC) device and/or a vector engine;
• a core having a register file that includes a zero-register;
• an input first in first out (FIFO) buffer and an output FIFO buffer providing communication into and out of the accelerator, respectively;
• and
• the processor configured to:
• turn a setting in a control and status register (CSR) of the core on and off,
• based on the setting being on and based on a first instruction of the core having the zero-register as a parameter thereof, executing the first instruction by either writing data of the first instruction to the input FIFO buffer or reading data of the first instruction from the output FIFO buffer, and
• based on the setting being off and based on a second instruction of the core having the zero-register as a parameter thereof, executing the second instruction by reading hardwired zeros from the zero-buffer.