Data clock recovery circuit
AssigneeMontage Electronics (Shanghai) Co., Ltd.
InventorsGuoKai Yi, YuanFei Nie
Life of this patent
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Abstract
A data clock recovery circuit includes a multi-task integrator, a controller, and an analog-to-digital converter, an equalizer, a decider, an error calculator, a phase detection estimator, a loop filter, and a phase interpolator sequentially coupled in series. The multi-task integrator is coupled between a coupling path of the phase interpolator and the loop filter, and selects one of a phase adjustment signal and a bias signal according to the mode selection signal to output to the phase interpolator. The controller is coupled to the multi-task integrator and is configured to generate a mode selection signal.
Claims12
A data clock recovery circuit, comprising:
- an analog-to-digital converter, an equalizer, a decider, an error calculator, a phase detection estimator, a loop filter, and a phase interpolator sequentially coupled in series;
- a multi-task integrator, coupled between a coupling path of the phase interpolator and the loop filter, and selecting one of a phase adjustment signal and a bias signal according to a mode selection signal to output to the phase interpolator;
- and
- a controller, coupled to the multi-task integrator and generating the mode selection signal by monitoring convergence of an equalizer coefficient.
Dependencies are inferred from the claim text.