Display device
AssigneeJapan Display Inc.
InventorHirotaka HAYASHI
Life of this patent
Estimating the term…
Abstract
To provide a technology that can increase an amplitude of a pixel electrode with respect to an amplitude of a source line without reducing the number of pixels in one row in a display device that adopts pixels including a boosting circuit. In a display device, the number of signal lines is doubled, and signal lines are separately provided for pixels in odd-numbered rows and pixels in adjacent even-numbered rows. Two rows are driven during the time of one horizontal period by simultaneously driving scanning lines in an odd-numbered row and an even-numbered row, and performing writing to pixels in the odd-numbered row and pixels in the adjacent even-numbered row. The one horizontal period can be thereby apparently halved.
Claims6
A display device comprising:
- a plurality of pixels arranged in a matrix manner;
- a first scanning line, a second scanning line, a third scanning line, and a fourth scanning line extending in a first direction and arranged in a second direction intersecting the first direction;
- and
- a first signal line and a second signal line extending in the second direction and arranged in the first direction,
- the plurality of pixels including a first pixel and a second pixel that is adjacent in the second direction to the first pixel,
- the first pixel including a first transistor, a second transistor, a third transistor, and a first common electrode and a first pixel electrode sandwiching a liquid crystal, the first common electrode being supplied with a reference potential,
- a gate of the first transistor being connected to the second scanning line, one of a source and a drain of the first transistor being connected to the first signal line, and other one of the source and the drain of the first transistor being connected to the first pixel electrode via a first capacitive element,
- a gate of the second transistor being connected to the first scanning line, one of a source and a drain of the second transistor being connected to the first signal line, and other one of the source and the drain of the second transistor being connected to the first pixel electrode,
- a gate of the third transistor being connected to the first scanning line, one of a source and a drain of the third transistor being connected to other one of the source and the drain of the first transistor, and other one of the source and the drain of the third transistor being connected to the first common electrode,
- the second pixel including a fourth transistor, a fifth transistor, a sixth transistor, and a second common electrode and a second pixel electrode sandwiching the liquid crystal, the second common electrode being supplied with the reference potential,
- a gate of the fourth transistor being connected to the fourth scanning line, one of a source and a drain of the fourth transistor being connected to the second signal line, and other one of the source and the drain of the fourth transistor being connected to the second pixel electrode via a second capacitive element,
- a gate of the fifth transistor being connected to the third scanning line, one of a source and a drain of the fifth transistor being connected to the second signal line, and other one of the source and the drain of the fifth transistor being connected to the second pixel electrode, and
- a gate of the sixth transistor being connected to the third scanning line, one of a source and a drain of the sixth transistor being connected to other one of the source and the drain of the fourth transistor, and other one of the source and the drain of the sixth transistor being connected to the second common electrode.
A display device comprising:
- a plurality of pixels arranged in a matrix manner;
- a first scanning line, a second scanning line, and a third scanning line extending in a first direction and arranged in a second direction intersecting the first direction;
- and
- a first signal line and a second signal line extending in the second direction and arranged in the first direction,
- the plurality of pixels including a first pixel and a second pixel arranged so as to be adjacent to each other in the second direction,
- the first pixel including a first transistor, a second transistor, a third transistor, and a first common electrode and a first pixel electrode sandwiching a liquid crystal, the first common electrode being supplied with a reference potential,
- a gate of the first transistor being connected to the second scanning line, one of a source and a drain of the first transistor being connected to the first signal line, and other one of the source and the drain of the first transistor being connected to the first pixel electrode via a first capacitive element,
- a gate of the second transistor being connected to the first scanning line, one of a source and a drain of the second transistor being connected to the first signal line, and other one of the source and the drain of the second transistor being connected to the first pixel electrode,
- a gate of the third transistor being connected to the first scanning line, one of a source and a drain of the third transistor being connected to other one of the source and the drain of the first transistor, and other one of the source and the drain of the third transistor being connected to the first common electrode,
- the second pixel including a fourth transistor, a fifth transistor, a sixth transistor, and a second common electrode and a second pixel electrode sandwiching the liquid crystal, the second common electrode being supplied with the reference potential,
- a gate of the fourth transistor being connected to the third scanning line, one of a source and a drain of the fourth transistor being connected to the second signal line, and other one of the source and the drain of the fourth transistor being connected to the second pixel electrode via a second capacitive element,
- a gate of the fifth transistor being connected to the second scanning line, one of a source and a drain of the fifth transistor being connected to the second signal line, and other one of the source and the drain of the fifth transistor being connected to the second pixel electrode, and
- a gate of the sixth transistor being connected to the second scanning line, one of a source and a drain of the sixth transistor being connected to other one of the source and the drain of the fourth transistor, and other one of the source and the drain of the sixth transistor being connected to the second common electrode.
Dependencies are inferred from the claim text.