Advanced fault attack detecting device using fault state propagation
AssigneeSamsung Electronics Co., Ltd.
InventorsKi Hong KIM, Dongsoo LEE
Life of this patent
Estimating the term…
Abstract
A fault detection circuit includes a logic circuit, and a compare circuit that detects whether a fault is generated in the logic circuit. The logic circuit includes a logic gate circuit including at least one sub logic gate circuit having a multi-bit signal as an input/output, and a flip-flop circuit electrically connected to the logic gate circuit. The flip-flop circuit includes at least one sub flip-flop circuit that latches and outputs data of a signal which the at least one sub logic gate circuit outputs. The compare circuit compares an output signal of the logic circuit and a fault state signal to generate a comparison result and detects whether the fault is generated in the logic circuit, based on the comparison result.
Claims20
A fault detection circuit comprising:
- a logic circuit;
- and
- a compare circuit configured to detect whether a fault is generated in the logic circuit,
- wherein the logic circuit includes:
- a logic gate circuit including at least one sub logic gate circuit having a multi-bit signal including a plurality of bits as an input/output;
- and
- a flip-flop circuit electrically connected to the logic gate circuit,
- wherein the flip-flop circuit includes:
- at least one sub flip-flop circuit configured to latch and output data of a signal which the at least one sub logic gate circuit outputs, and
- wherein the compare circuit is configured to:
- compare an output signal of the logic circuit and a fault state signal to generate a comparison result;
- and
- detect whether the fault is generated in the logic circuit, based on the comparison result.
A fault detection circuit comprising:
- a first logic circuit configured to receive a lower bit signal of a multi-bit input signal including a plurality of bits and to perform a logic operation on the lower bit signal;
- a second logic circuit configured to receive an upper bit signal of the multi-bit input signal and to perform a logic operation on the upper bit signal, wherein the second logic circuit operates in synchronization with the first logic circuit in a lockstep method to detect whether a fault is generated in the first logic circuit;
- and
- a compare circuit configured to output a comparison result obtained by comparing a multi-bit output signal of a plurality of bits, which includes output signals of the first logic circuit and the second logic circuit as a lower bit signal and an upper bit signal, with a fault state signal and to detect whether a fault is generated in the first logic circuit, based on the comparison result,
- wherein the first logic circuit includes:
- at least one logic gate circuit including a logic gate;
- and
- at least one flip-flop circuit including a flip-flop electrically connected to the at least one logic gate circuit, and
- wherein the flip-flop circuit includes:
- at least one D flip-flop configured to latch and output an output received from the at least one logic gate circuit based on a clock signal;
- and
- a clock gating circuit configured to hold data of an output signal of the at least one D flip-flop when the output signal of the at least one D flip-flop is the fault state signal.
A method of detecting a fault in a logic circuit, the method comprising:
- defining a signal as a true state, a false state, or a fault state;
- latching a fault state signal input to at least one sub flip-flop circuit included in the logic circuit when a fault is generated in at least one sub logic gate circuit included in the logic circuit;
- propagating the fault state signal in the logic circuit;
- outputting, at the logic circuit, an output signal;
- and
- outputting, at a compare circuit, a comparison result obtained by comparing the fault state signal and the output signal and detecting whether a fault is generated based on the comparison result.
Dependencies are inferred from the claim text.