Semiconductor package having high-voltage stacked transistors and method of making the same

A method for fabricating a semiconductor package, the method comprising the steps of:

• providing a lead frame comprising
• a die paddle,
• a source paddle, and
• a gate paddle;
• mounting a first high-voltage field-effect transistor (FET) on the die paddle, the first high-voltage FET comprising:
• a source electrode and a gate electrode on a front surface of the first high-voltage FET;
• and
• a drain electrode on a back surface of the first high-voltage FET;
• attaching a source clip connecting the source electrode of the first high-voltage FET to the source paddle;
• attaching a gate clip to the gate paddle, the gate clip comprising:
• a first island;
• and
• a second island;
• mounting a second high-voltage FET on the source clip, the second high-voltage FET being flipped, the second high-voltage FET comprising:
• a source electrode and a gate electrode on a front surface of the second high-voltage FET;
• and
• a drain electrode on a back surface of the second high-voltage FET;
• applying a drain connection member connecting the drain electrode of the second high-voltage FET to the die paddle;
• forming a molding encapsulation enclosing the first high-voltage FET, the source clip, the gate clip, the second high-voltage FET, at least a majority portion of the drain connection member, and a majority portion of the lead frame;
• and
• applying a singulation process separating the semiconductor package from adjacent semiconductor packages;
• wherein a bottom surface of the first island of the gate clip is attached to the gate electrode of the first high-voltage FET;
• and
• wherein a top surface of the second island of the gate clip is attached to the gate electrode of the second high-voltage FET.