Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• an interposer substrate;
• and
• a chip stack on the interposer substrate,
• wherein the chip stack includes:
• a first semiconductor chip;
• a second semiconductor chip on the first semiconductor chip;
• connection terminals between the first semiconductor chip and the second semiconductor chip and electrically connecting the first semiconductor chip and the second semiconductor chip;
• and
• a thermal conductive layer between the first semiconductor chip and the second semiconductor chip,
• wherein the thermal conductive layer is horizontally spaced apart from the connection terminals, and
• wherein the thermal conductive layer includes carbon (C).

A method of manufacturing a semiconductor package, the method comprising:

• providing a first semiconductor chip having a central region and an edge region surrounding the central region, the first semiconductor chip including chip pads on a first surface of the first semiconductor chip on the central region;
• electrically connecting connection terminals to the chip pads on the first surface of the first semiconductor chip;
• applying a non-conductive layer surrounding the connection terminals;
• performing a laser irradiation process on the non-conductive layer to form a thermal conductive layer;
• positioning a second semiconductor chip on the non-conductive layer and the thermal conductive layer;
• and
• performing a thermocompression process on the second semiconductor chip to bond the first semiconductor chip and the second semiconductor chip,
• wherein the thermal conductive layer includes laser induced graphene (LIG).

A semiconductor package comprising:

• a substrate including a plurality of vias passing therethrough;
• a chip stack mounted on the substrate;
• and
• a molding layer surrounding the chip stack on the substrate,
• wherein the chip stack includes:
• a first semiconductor chip on the substrate;
• a second semiconductor chip on the first semiconductor chip;
• connection terminals between the first semiconductor chip and the second semiconductor chip and electrically connecting the first semiconductor chip and the second semiconductor chip;
• and
• an adhesive layer between the first semiconductor chip and the second semiconductor chip and surrounding the connection terminals,
• wherein the adhesive layer includes:
• a thermal conductive layer in contact with an upper surface of the first semiconductor chip and a lower surface of the second semiconductor chip, the thermal conductive layer spaced apart from the connection terminals;
• and
• a non-conductive layer surrounding the thermal conductive layer and surrounding the connection terminals, wherein a thermal conductivity of the thermal conductive layer is at least 40 times greater than a thermal conductivity of the non-conductive layer.