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A semiconductor device, comprising:

• a first metal level including first metal lines;
• a second metal level including second metal lines;
• and
• a via level between the first metal level and the second metal level, the via level including:
• a first dielectric layer on the first metal lines;
• a second dielectric layer on the first dielectric layer;
• and
• vias extending through the first dielectric layer and the second dielectric layer;
• wherein the vias include:
• a top portion in the second dielectric layer having a first width;
• and
• a bottom portion in the first dielectric layer having a second width, the second width being greater than the first width;
• and
• wherein the second metal lines include end portions separated by a dielectric pillar.

A semiconductor device, comprising:

• a first metal level including first metal lines;
• a second metal level including second metal lines;
• and
• a via level between the first metal level and the second metal level, the via level including:
• a first dielectric layer on the first metal lines;
• a second dielectric layer on the first dielectric layer;
• and
• linerless vias extending through the first dielectric layer and the second dielectric layer;
• wherein the linerless vias include:
• a top portion in the second dielectric layer having a first width;
• and
• a bottom portion in the first dielectric layer having a second width, the second width being greater than the first width and the bottom portion directly contacting a top surface of one of the first metal lines;
• and
• wherein the second metal lines include end portions separated by a dielectric pillar, the dielectric pillar having a width between the end portions.