Depth image sensor having a charge-domain architecture

An image sensor comprising a readout circuit and a plurality of pixels formed in and/or on a substrate of the sensor, such that at least one of the pixels is a depth pixel, each depth pixel comprising:

• a photosensitive region of the substrate,
• a first and a second controllable storage zones, each controllable storage zone comprising:
• an electric charge flow path extending vertically in the substrate vertically in line with the photosensitive region and comprising a memory region which is a potential well and a barrier which is an electric potential barrier interposed between the memory region and the photosensitive region,
• a transfer gate extending vertically in the substrate vertically in line with the photosensitive region, facing the barrier,
• a reverse transfer gate extending vertically in the substrate facing the barrier and facing an upper part of the photosensitive region,
• an additional electric charge flow path extending vertically in the substrate between the respective transfer gates (111) of the first and second controllable storage zones, vertically in line with the photosensitive region, comprising a collection zone which is an electric potential well and a collection channel which is an electric potential barrier interposed between the collection zone and the photosensitive region,
• wherein the readout circuit comprises a sense node electrically connected to the collection zone and is configured to successively:
• applying, in each controllable storage zone, a periodic pulse train to the transfer gate during a sampling phase common to the first and second controllable storage zones, so as to make electric charges flow from the photosensitive region to the memory region during the pulses, wherein the respective pulse trains of the first and second controllable storage zones are phase shifted relative to one another, and have the same period,
• performing a first reset of the sense node,
• performing a first charge evacuation during which the transfer gates of the first and second controllable storage zones, and the reverse transfer gate of the first controllable storage zone are activated so as to make the electric charges flow from the memory region of the first controllable storage zone to the collection zone,
• reading an electric potential Vsig1 of the sense node,
• performing a second reset of the sense node,
• performing a second charge evacuation during which the transfer gates of the first and second controllable storage zones, and the reverse transfer gate of the second controllable storage zone are activated so as to make the electric charges flow from the memory region of the second controllable storage zone to the collection zone,
• reading an electric potential Vsig2 of the sense node.