Semiconductor device

A semiconductor device comprising:

• a SiC semiconductor layer that includes an active region and a terminal region that surrounds the active region;
• a plurality of transistor cells that are formed in cell regions of the active region of the SiC semiconductor layer and that are subjected to ON/OFF control by means of a predetermined control voltage;
• a gate electrode that faces a channel region of the transistor cells in which a channel is formed when turned on;
• a gate metal that includes a gate pad that is exposed at a topmost surface for electric connection with an outside, the gate pad being physically separated from the gate electrode and being electrically connected to the gate electrode;
• a built-in resistor that electrically connects the gate metal and the gate electrode together, the built-in resistor being made of a material that has a resistance value that is larger than the gate metal;
• and
• a source metal,
• wherein a p− type region is formed in the surface portion of the SiC semiconductor layer in regions other than the cell regions in the active region,
• a p+ type region is formed in a surface portion of the p− type region,
• the p+ type region selectively exposes the p− type part of the p− type region at the SiC surface in a region of the SiC semiconductor layer facing the built-in resistor,
• the transistor cell includes a p+ type body contact region, and
• the p+ type body contact region is fixed at ground potential along with the source metal.

A semiconductor device comprising:

• a SiC semiconductor layer that includes an active region and a terminal region that surrounds the active region;
• a plurality of transistor cells that are formed in cell regions of the active region of the SiC semiconductor layer and that are subjected to ON/OFF control by means of a predetermined control voltage;
• a gate electrode that faces a channel region of the transistor cells in which a channel is formed when turned on;
• a gate metal that includes a gate pad that is exposed at a topmost surface for electric connection with an outside, the gate pad being physically separated from the gate electrode and being electrically connected to the gate electrode;
• and
• a built-in resistor that electrically connects the gate metal and the gate electrode together, the built-in resistor being made of a material that has a resistance value that is larger than the gate metal,
• wherein a p− type region is formed in the surface portion of the SiC semiconductor layer in regions other than the cell regions in the active region,
• a p+ type region is formed in a surface portion of the p− type region,
• the p+ type region selectively exposes the p− type part of the p− type region at the SiC surface in a region of the SiC semiconductor layer facing the built-in resistor,
• the semiconductor device further comprising:
• a gate finger that extends from the gate metal,
• wherein the gate metal is selectively formed at a part of a peripheral edge of the active region and near the boundary with the terminal region,
• the gate finger extends from the formation position of the gate pad in a direction along the peripheral edge of the active region and in a direction toward the inside of the active region,
• in the active region, inner cell regions and outer cell regions are formed in parts partitioned by a plurality of gate fingers that extend in mutually different directions with the gate metal therebetween, and are formed in a region outside the gate finger, respectively.

A semiconductor device comprising:

• a SiC semiconductor layer that includes an active region and a terminal region that surrounds the active region;
• a plurality of transistor cells that are formed in cell regions of the active region of the SiC semiconductor layer and that are subjected to ON/OFF control by means of a predetermined control voltage;
• a gate electrode that faces a channel region of the transistor cells in which a channel is formed when turned on;
• a gate metal that includes a gate pad that is exposed at a topmost surface for electric connection with an outside, the gate pad being physically separated from the gate electrode and being electrically connected to the gate electrode;
• and
• a built-in resistor that electrically connects the gate metal and the gate electrode together, the built-in resistor being made of a material that has a resistance value that is larger than the gate metal,
• wherein a p− type region is formed in the surface portion of the SiC semiconductor layer in regions other than the cell regions in the active region,
• a p+ type region is formed in a surface portion of the p− type region,
• the p+ type region selectively exposes the p− type part of the p− type region at the SiC surface in a region of the SiC semiconductor layer facing the built-in resistor, and
• both the gate electrode and the built-in resistor are made of p type polysilicon.

A semiconductor device comprising:

• a SiC semiconductor layer that includes an active region and a terminal region that surrounds the active region;
• a plurality of transistor cells that are formed in cell regions of the active region of the SiC semiconductor layer and that are subjected to ON/OFF control by means of a predetermined control voltage;
• a gate electrode that faces a channel region of the transistor cells in which a channel is formed when turned on;
• a gate metal that includes a gate pad that is exposed at a topmost surface for electric connection with an outside, the gate pad being physically separated from the gate electrode and being electrically connected to the gate electrode;
• and
• a built-in resistor that electrically connects the gate metal and the gate electrode together, the built-in resistor being made of a material that has a resistance value that is larger than the gate metal,
• wherein a p− type region is formed in the surface portion of the SiC semiconductor layer in regions other than the cell regions in the active region,
• a p+ type region is formed in a surface portion of the p− type region,
• the p+ type region selectively exposes the p− type part of the p− type region at the SiC surface in a region of the SiC semiconductor layer facing the built-in resistor, and
• the cell region includes an annular outer cell region that is formed along the peripheral edge of the active region.