Silicon-oxide-nitride-oxide-silicon type non-volatile memory
AssigneeeMemory Technology Inc.
InventorsChia-Jung HSU, Chun-Hsiao LI, Chang-Chun LUNG
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Abstract
A SONOS type non-volatile memory includes a memory cell array. The memory cell array includes a memory cell area and a non-memory cell area. The connection relationship between SONOS memory cells in the memory cell area are specially designed, and the memory cell array is divided into multiple sections. When the erase action is performed, only one section in the memory cell array is erased, but the other sections are not erased. Furthermore, isolation transistors are provided in the non-memory cell area to isolate the well lines and the bit line. Consequently, the SONOS memory cells can be operated normally.
Claims15
A silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory comprising a memory cell array, the memory cell array being formed on a semiconductor substrate and comprising:
- a first row comprising a plurality of SONOS memory cells, which are formed in a first well region, wherein first terminals of the plurality of SONOS memory cells in the first row are electrically connected to a first source line, second terminals of the plurality of SONOS memory cells in the first row are electrically connected to a first bit line, control gate terminals of the plurality of SONOS memory cells in the first row are electrically connected to a control line, and select gate terminals of the plurality of SONOS memory cells in the first row are respectively connected to a plurality of word lines;
- a first isolation transistor formed in the first well region and located at a first side of the first row, wherein a first drain/source terminal of the first isolation transistor is electrically connected to a first well line, a second drain/source terminal of the first isolation transistor is electrically connected to the first bit line, an isolation gate terminal of the first isolation transistor is electrically connected to an isolation gate line, and a body terminal of the first isolation transistor is electrically connected to the first well region, wherein the first well line is electrically connected to the first well region;
- a second row comprising a plurality of SONOS memory cells, which are formed in a second well region, wherein first terminals of the plurality of SONOS memory cells in the second row are electrically connected to a second source line, second terminals of the plurality of SONOS memory cells in the second row are electrically connected to a second bit line, control gate terminals of the plurality of SONOS memory cells in the second row are electrically connected to the control line, and select gate terminals of the plurality of SONOS memory cells in the second row are respectively connected to the plurality of word lines;
- and
- a second isolation transistor formed in the second well region and located at a first side of the second row, wherein a first drain/source terminal of the second isolation transistor is electrically connected to a second well line, a second drain/source terminal of the second isolation transistor is electrically connected to the second bit line, an isolation gate terminal of the second isolation transistor is electrically connected to the isolation gate line, and a body terminal of the second isolation transistor is electrically connected to the second well region, wherein the second well line is electrically connected to the second well region,
- wherein the first well region and the second well region are not in contact with each other.
Dependencies are inferred from the claim text.