Three-dimensional vertical nonvolatile memory device including memory cell strings, method of driving the same, and electronic apparatus including the same

A method of driving a three-dimensional vertical non-volatile memory device, the three-dimensional vertical non-volatile memory device including

• a channel layer extending in a first direction,
• a plurality of gate electrodes and a plurality of insulating spacers alternately arranged in the first direction, each of the plurality of gate electrodes and each of the plurality of insulating spacers extending in a second direction crossing the first direction,
• an electrochemical layer extending in the first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of insulating spacers, and
• a blocking layer extending in the first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of insulating spacers, the blocking layer including a charge trap layer that is configured to trap charges according to a voltage applied to each of the plurality of gate electrodes, the method comprising:
• applying a negative (−) program voltage to a first gate electrode of the plurality of gate electrodes;
• moving and trapping electrons in a partial area of the charge trap layer adjacent in the second direction to the first gate electrode;
• and
• moving ions in a partial area of the channel layer adjacent in the second direction to the first gate electrode to a partial area of the electrochemical layer adjacent in the second direction to the first gate electrode so that the partial area of the channel layer has a first resistance.

An electronic apparatus comprising:

• a processing circuit;
• and
• a three-dimensional vertical non-volatile memory device,
• wherein the three-dimensional vertical non-volatile memory device comprises:
• a channel layer extending in a first direction;
• a plurality of gate electrodes and a plurality of insulating spacers alternately arranged in the first direction, each of the plurality of gate electrodes and each of the plurality of insulating spacers extending in a second direction crossing the first direction;
• an electrochemical layer extending in the first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of insulating spacers;
• and
• a blocking layer extending in the first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of insulating spacers,
• wherein the electrochemical layer and the channel layer are configured to move ions from the electrochemical layer to the channel layer or from the channel layer to the electrochemical layer according to a voltage applied to each of the plurality of gate electrodes, and
• the blocking layer includes a charge trap layer that extends in the first direction and is configured to trap charges according to the voltage applied to each of the plurality of gate electrodes.